CN117609139A - Host and server - Google Patents

Abstract

The embodiment of the invention provides a mainboard and a server, and relates to the technical field of computers. The main board comprises a host computer, a slave computer, a pull-up resistor, a switch module and a driving module. The host and the slave are connected through an enhanced serial peripheral interface bus. The enhanced serial peripheral interface bus comprises a chip selection signal wire, a pull-up resistor is arranged on the chip selection signal wire, a switch module is arranged on the chip selection signal wire and is positioned between the pull-up resistor and a host, and a driving module is electrically connected with the switch module. And the pull-up resistor is used for pulling up the chip selection signal in the chip selection signal line to be high level when the slave is powered on and the master is not powered on. The switch module is used for being disconnected when the slave machine is electrified and the host machine is not electrified, and conducting the chip selection signal line according to the conducting signal of the driving module after the host machine is electrified. And the driving module is used for controlling the switch module to be conducted based on the conduction signal when the host is powered on. The invention can effectively solve the problem of voltage leakage of the power domain of the host.

Description

Host and server

Technical Field

The invention relates to the technical field of computers, in particular to a host and a server.

Background

ESPI (Enhanced Serial Peripheral Interface ) bus is a communication bus developed by intel corporation in 2016 for communication between a platform CPU (Central Processing Unit ) and a peripheral management unit.

In some scenarios, the slave of the motherboard needs to be powered up first, while the motherboard is powered up later. However, in this case, the slave may drive the IO data line of the ESPI high, so that the voltage on the IO data line leaks through the inside of the host chip onto its power domain, thereby affecting the chip power-on timing and reducing the reliability of the chip.

Disclosure of Invention

The object of the present invention consists, for example, in providing a host and a server which are able to solve at least partially the technical problems mentioned above.

Embodiments of the invention may be implemented as follows:

in a first aspect, an embodiment of the present invention provides a motherboard, where the motherboard includes a host, a slave, a pull-up resistor, a switch module, and a driving module; the host computer is connected with the slave computer through an enhanced serial peripheral interface bus; the enhanced serial peripheral interface bus comprises a chip selection signal line, the pull-up resistor is arranged on the chip selection signal line, the switch module is arranged on the chip selection signal line and is positioned between the pull-up resistor and the host, and the drive module is electrically connected with the switch module;

the pull-up resistor is used for pulling up a chip selection signal in the chip selection signal line to be high level when the slave is powered on and the master is not powered on;

the switch module is used for being disconnected when the slave is electrified and the host is not electrified, and conducting the chip selection signal line according to the conducting signal of the driving module after the host is electrified;

and the driving module is used for controlling the switch module to be conducted based on the conduction signal when the host is powered on.

Optionally, the main board further comprises a power module; the power supply module is electrically connected with the host and the driving module respectively;

the power supply module is used for supplying power to the host so as to electrify the host;

and changing the conduction signal to be high level so that the driving module controls the switching module based on the conduction signal.

Optionally, the switch module includes a relay, and the conduction signal includes a current signal; the controlling the switch module to be turned on based on the on signal includes:

the driving module receives current from the power supply module when the host is powered on;

the driving module converts the current into the current signal;

and the driving module controls the relay to be conducted according to the current signal.

Optionally, the switch module includes a triode, and the conduction signal includes a level signal; the controlling the switch module to be turned on based on the on signal includes:

the driving module receives an electric signal from the power supply module when the host is powered on;

the driving module converts the electric signal into the level signal;

and the driving module controls the triode to be conducted according to the level signal.

Optionally, the switch module includes an isolation buffer, and the on signal includes an enable signal; the controlling the switch module to be turned on based on the on signal includes:

the driving module receives an electric signal from the power supply module when the host is powered on;

the driving module generates the enabling signal based on the electrical signal;

and the driving module controls the isolation buffer to be conducted according to the enabling signal.

Optionally, the enhanced serial peripheral interface bus further comprises a clock signal line;

the host generates a clock signal and sends the clock signal to the slave through the clock signal line;

the slave receives the clock signal and works based on the clock signal;

the clock signal line is used for transmitting the clock signal generated by the host to the slave.

Optionally, the enhanced serial peripheral interface bus further comprises a data signal line;

the data signal line is used for transmitting the data sent by the host to the slave;

and/or transmitting data sent by the slave to the host.

Optionally, the enhanced serial peripheral interface bus further includes a reset signal line;

the host generates a reset signal and sends the reset signal to the slave computer through the reset signal line;

the slave receives the reset signal and resets based on the reset signal;

the reset signal line is used for transmitting a reset signal generated by the host to the slave.

Optionally, the master includes a plurality of chip select signal interfaces and a plurality of slaves; each slave is connected with one chip selection signal interface through one chip selection signal line;

each chip selection signal line is provided with the switch module and the pull-up resistor; the switch module is located between the pull-up resistor and the host.

In a second aspect, an embodiment of the present invention provides a server, where the server includes the motherboard of any one of the above embodiments.

The beneficial effects of the embodiment of the invention include, for example:

by arranging the pull-up resistor on the chip selection signal line, when the slave is powered on and the host is not powered on, the pull-up resistor can pull up the chip selection signal in the chip selection signal line to be high level. Therefore, the phenomenon that the slave drives the IO data line of the ESPI to be high level is avoided, the voltage on the IO data line leaks to the power domain of the host chip through the inside of the host chip, and the reliability of the main board chip is further improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a conventional motherboard architecture according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a motherboard architecture with a pull-up resistor and a switch module according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a motherboard architecture with a power module according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a motherboard architecture including a plurality of slaves according to an embodiment of the present invention.

Icon: 01-a motherboard; 11-a host; 12-slave; 13-pull-up resistor; 14-a switch module; 15-a drive module; a 16-power module; 21-an enhanced serial peripheral interface bus; 211-chip select signal lines; 212-a clock signal line; 213-data signal lines; 214-reset signal line.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.

Furthermore, the terms "first," "second," and the like, if any, are used merely for distinguishing between descriptions and not for indicating or implying a relative importance.

It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.

ESPI (Enhanced Serial Peripheral Interface, i.e., enhanced serial peripheral interface) bus is a communication bus developed by Intel corporation in 2016 for communication between an x86 platform CPU (Central Processing Unit ) and external management units such as BMC systems, EC systems, and SIO (super input output chips). As shown in fig. 1, in the conventional motherboard design, a single master is used to connect to a single slave. According to the EPSI bus protocol, when the host and the slave are connected in one-to-one manner, the bus data signal ESPI_IO [1] is multiplexed as an alarm signal. When the level of the ESPI_CS# signal on the bus is pulled low, the slave must either drive the alarm signal high or release it as high.

However, if the slave is powered up first and the master is not yet powered up, the ESPI_CS# signal is not driven, and the level is low. Then, according to the protocol requirements, the slave may drive espi_io [1] to high level, and the voltage on the data line leaks to its power domain through the inside of the host chip, which affects the power-on timing of the chip and also reduces the reliability of the chip. For example, when the slave is a BMC or an EC and the BMC or the EC is a whole board management unit, the slave may be powered on first.

Based on the above situation, the invention provides a host and a server, which can effectively relieve the technical problems that the voltage on the data line, which is caused by the fact that the slave is powered on first and the host is not powered on yet, leaks to the power domain of the host through the inside of the host chip, so that the power-on time sequence of the chip is influenced and the reliability of the chip is reduced.

As shown in fig. 2, the present invention provides a motherboard 01, where the motherboard 01 includes a master 11, a slave 12, a pull-up resistor 13, a switch module 14, and a driving module 15. The master 11 and the slave 12 are connected by an enhanced serial peripheral interface bus 21. The enhanced serial peripheral interface bus 21 includes a chip select signal line 211, a pull-up resistor 13 is disposed on the chip select signal line 211, a switch module 14 is disposed on the chip select signal line 211 and between the pull-up resistor 13 and the host 11, and a driving module 15 is electrically connected to the switch module 14.

The pull-up resistor 13 is used for pulling up the chip select signal in the chip select signal line 211 to a high level when the slave 12 is powered up and the master 11 is not powered up.

The switch module 14 is configured to be turned off when the slave 12 is powered on and the host 11 is not powered on, and to turn on the chip select signal line 211 according to the on signal of the driving module 15 after the host 11 is powered on.

The driving module 15 is configured to control the switch module 14 to be turned on based on the on signal when the host 11 is powered on.

The motherboard 01 may be a processing system of a computer, a microcomputer, or the like. The main board 01 includes a master 11 and a slave 12, and the slave 12 may be various, such as a BMC, an EC, a Super io, and an MCU (Microcontroller Unit, micro control unit), and the like. The master 11 and the slave 12 are connected by an enhanced serial peripheral interface bus 21 (i.e., ESPI bus). The enhanced serial peripheral interface bus 21 may include a plurality of signal lines, such as chip select signal lines 211, to enable the master 11 to communicate with the slaves 12 in a serial fashion to exchange information.

The pull-up resistor 13 is arranged on the chip selection signal line 211, and in the case that the slave 12 is powered on first and the host 11 is not powered on, the pull-up resistor 13 can pull up the chip selection signal in the chip selection signal line 211 to be at a high level, so that the voltage leakage from the inside of the chip of the host 11 to the power domain caused by the fact that the slave 12 drives the IO signal to be at the high level is avoided.

The switch module 14 is disposed on the chip select signal line 211 and located between the pull-up resistor 13 and the host 11, and can be used to control the on/off of the host 11 and the slave 12 at two ends of the chip select signal line 211. The switch module 14 is turned off when the slave 12 is powered on and the master 11 is not powered on; when the power-up of the host 11 is completed, the chip select signal line 211 is turned on by the transmitted on signal of the driving module 15. The switch module 14 is driven by the driving module 15, and when the switch module 14 is required to be switched from the off state to the on state, the driving module 15 can apply a conducting signal to the switch module 14 for closing the switch module 14, so that the switch module 14 is closed and conducted.

Optionally, as shown in fig. 3, the motherboard 01 further includes a power module 16. The power module 16 is electrically connected to the host 11 and the driving module 15, respectively.

The power module 16 is configured to supply power to the host 11, so that the host 11 is powered on. And changing the on signal to a high level so that the driving module 15 controls the switching module 14 based on the on signal.

In one embodiment, a power module 16 may be provided, such that the power module 16 is connected to the host 11 and the driving module 15, respectively. When the host 11 needs to be powered on, after the Power module 16 finishes supplying Power to the host 11, the Power Good signal is pulled high, and the Power module 16 changes the on signal to a high level, so that the driving module 15 controls the switch module 14 to be turned on based on the on signal. Finally, the effect that the switch module 14 is disconnected before the host 11 is powered up is achieved, and the switch module 14 is conducted after the host 11 is powered up is achieved.

Optionally, the switch module 14 comprises a relay, and the on signal comprises a current signal. The controlling the switch module 14 to be turned on based on the on signal includes:

the drive module 15 receives current from the power module 16 when the power-up of the host 11 is completed.

The drive module 15 converts the current into the current signal. The driving module 15 controls the relay to be conducted according to the current signal.

The relay is an electric control device that gives a prescribed input amount and holds it for a sufficient time to cause a predetermined step change in the controlled amount in the output circuit. When the input amount is reduced to a certain degree and kept for a long enough time, the state is restored to the original state. Relays include electromagnetic relays, solid state relays, time relays, and the like. The relay may be used in a circuit as a switch, so the present invention may employ a relay as the switch module 14. When the power-on of the host 11 is completed, the driving module 15 receives the current from the power module 16, converts the current into a current signal, and controls the relay to be turned on through the current signal.

Optionally, the switching module 14 comprises a transistor, and the on signal comprises a level signal. The controlling the switch module 14 to be turned on based on the on signal includes:

the driving module 15 receives an electrical signal from the power module 16 when the power-up of the host 11 is completed.

The drive module 15 converts the electrical signal into the level signal. The driving module 15 controls the transistor to be turned on according to the level signal.

The appearance of the switching triode (Switch transistor) is the same as that of a common triode, and the switching triode works in a cut-off area and a saturation area and is equivalent to cut-off and conduction of a circuit. It has an effect of completing the turn-off and turn-on, and thus is widely used in various switching circuits such as switching power supply circuits, driving circuits, high-frequency oscillation circuits, analog-to-digital conversion circuits, pulse circuits, output circuits, and the like.

Thus, as an alternative embodiment, a transistor may be employed as the switching module 14. When the host 11 is powered on, the power module 16 sends an electrical signal to the driving module 15, the driving module 15 converts the electrical signal into a level signal, and then the transistor is controlled to be turned on through the level signal. In particular, the level signal may be selected to be high or low according to the structure and connection of the transistors, which is not particularly limited in the present invention.

Optionally, the switch module 14 includes an isolation buffer, and the on signal includes an enable signal. The controlling the switch module 14 to be turned on based on the on signal includes:

the driving module 15 receives an electrical signal from the power module 16 when the power-up of the host 11 is completed.

The drive module 15 generates the enable signal based on the electrical signal. The driving module 15 controls the isolation buffer to be conducted according to the enabling signal.

In another alternative embodiment, an isolation buffer may also be employed as the switch module 14. The isolation buffer may have an enabling function, when the host 11 is powered on, the power module 16 sends an electrical signal to the driving module 15, the driving module 15 converts the electrical signal into an enabling signal, and the isolation buffer is turned on by the enabling signal, so that the chip selection signal line 211 between the host 11 and the slave 12 can communicate.

Optionally, as shown in fig. 2, the enhanced serial peripheral interface bus 21 further includes a clock signal line 212. The master 11 generates a clock signal and transmits the clock signal to the slave 12 via the clock signal line 212.

The slave 12 receives the clock signal and operates based on the clock signal. A clock signal line 212 for transmitting a clock signal generated by the master 11 to the slave 12.

Optionally, still taking fig. 2 as an example, the enhanced serial peripheral interface bus 21 further includes a data signal line 213.

A data signal line 213 for transmitting data from the master 11 to the slave 12. And/or to transmit data sent from the slave 12 to the host 11.

Optionally, referring to fig. 2, the enhanced serial peripheral interface bus 21 further includes a reset signal line 214.

The master 11 generates a reset signal and transmits the reset signal to the slave 12 via the reset signal line 214.

The slave 12 receives the reset signal and resets based on the reset signal. A reset signal line 214 for transmitting a reset signal generated by the master 11 to the slave 12.

When the master 11 and the slave 12 normally communicate, the master 11 transmits a clock signal (espi_clk) over the clock signal line 212 so that the data bit output of the master 11 is synchronized with the bit sampling of the slave 12. Since one bit of data is transmitted every clock cycle, the speed of data transmission is determined by the frequency of the clock signal.

The master 11 and the slave 12 communicate data via a data signal line 213, and the data signal line 213 transmits data transmitted from the master 11 to the slave 12 and data transmitted from the slave 12 to the master 11, respectively.

The master 11 may also send a generated RESET signal (espi_reset#) to the slave 12 via the RESET signal line 214 to RESET the slave 12.

Alternatively, as shown in fig. 4, the master 11 includes a plurality of chip select signal interfaces and a plurality of slaves 12; each slave 12 is connected to one of the chip select signal interfaces via one of the chip select signal lines 211.

Each chip select signal line 211 is provided with a switch module 14 and a pull-up resistor 13. The switch module 14 is located between the pull-up resistor 13 and the host 11.

The master 11 may communicate with a plurality of slaves 12, and fig. 4 is only exemplary, and in particular cases there may be more slaves 12 in communication with the master 11. Each slave 12 may be connected to the master 11 through a chip select signal line 211 with a pull-up resistor 13 and a switch module 14, and for each chip select signal line 211, the master 11 is required to provide a separate interface (i.e., chip select signal interface) connection. For the clock signal line 212, the data signal line 213, and the reset signal line 214, it is not necessary that the host 11 provide a separate signal line interface, and the signal lines may be separated from the clock signal line 212, the data signal line 213, and the reset signal line 214 in the form of "bus-lines", respectively, so that the host 11 communicates clock signals, data, and reset signals with the respective slaves 12.

The slave 12 cannot directly communicate with the slave 12.

Based on the same inventive concept, the invention also provides a server, and the server can realize the functions realized by the main board when in operation.

The invention at least comprises the following beneficial effects:

1. by arranging the pull-up resistor on the chip selection signal line, when the slave is powered on and the host is not powered on, the pull-up resistor can pull up the chip selection signal in the chip selection signal line to be high level. Therefore, the phenomenon that the slave drives the IO data line of the ESPI to be high level is avoided, the voltage on the IO data line leaks to the power domain of the host chip through the inside of the host chip, and the reliability of the main board chip is further improved.

2. By arranging the switch module on the chip selection signal line, the chip selection signals of the master machine and the slave machine can be isolated when the switch module is opened, and the chip selection signals are conducted when the switch module is closed. The chip selection signal of the slave side can not leak high level to the power domain of the host before the host is powered on, and can be controlled by the host after the host is powered on. At this time, since the host is powered up, even if the IO signal line has a high level, the power supply of the IO signal line is not affected.

In the several embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other manners. The apparatus embodiments described above are merely illustrative, for example, of the flowcharts and block diagrams in the figures that illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, functional modules in the embodiments of the present invention may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (10)

1. The mainboard is characterized by comprising a host computer, a slave computer, a pull-up resistor, a switch module and a driving module; the host computer is connected with the slave computer through an enhanced serial peripheral interface bus; the enhanced serial peripheral interface bus comprises a chip selection signal line, the pull-up resistor is arranged on the chip selection signal line, the switch module is arranged on the chip selection signal line and is positioned between the pull-up resistor and the host, and the drive module is electrically connected with the switch module;

the pull-up resistor is used for pulling up a chip selection signal in the chip selection signal line to be high level when the slave is powered on and the master is not powered on;

the switch module is used for being disconnected when the slave is electrified and the host is not electrified, and conducting the chip selection signal line according to the conducting signal of the driving module after the host is electrified;

and the driving module is used for controlling the switch module to be conducted based on the conduction signal when the host is powered on.

2. The motherboard of claim 1, wherein the motherboard further comprises a power module; the power supply module is electrically connected with the host and the driving module respectively;

the power supply module is used for supplying power to the host so as to electrify the host;

and changing the conduction signal to be high level so that the driving module controls the switching module based on the conduction signal.

3. The motherboard of claim 2, wherein the switch module comprises a relay, the on signal comprising a current signal; the controlling the switch module to be turned on based on the on signal includes:

the driving module receives current from the power supply module when the host is powered on;

the driving module converts the current into the current signal;

and the driving module controls the relay to be conducted according to the current signal.

4. The motherboard of claim 2, wherein the switch module comprises a transistor, the turn-on signal comprising a level signal; the controlling the switch module to be turned on based on the on signal includes:

the driving module receives an electric signal from the power supply module when the host is powered on;

the driving module converts the electric signal into the level signal;

and the driving module controls the triode to be conducted according to the level signal.

5. The motherboard of claim 2, wherein the switch module comprises an isolation buffer, the on signal comprises an enable signal; the controlling the switch module to be turned on based on the on signal includes:

the driving module receives an electric signal from the power supply module when the host is powered on;

the driving module generates the enabling signal based on the electrical signal;

and the driving module controls the isolation buffer to be conducted according to the enabling signal.

6. The motherboard of claim 1, wherein the enhanced serial peripheral interface bus further comprises a clock signal line;

the host generates a clock signal and sends the clock signal to the slave through the clock signal line;

the slave receives the clock signal and works based on the clock signal;

the clock signal line is used for transmitting the clock signal generated by the host to the slave.

7. The motherboard of claim 1, wherein the enhanced serial peripheral interface bus further comprises a data signal line;

the data signal line is used for transmitting the data sent by the host to the slave;

and/or transmitting data sent by the slave to the host.

8. The motherboard of claim 1, wherein the enhanced serial peripheral interface bus further comprises a reset signal line;

the host generates a reset signal and sends the reset signal to the slave computer through the reset signal line;

the slave receives the reset signal and resets based on the reset signal;

the reset signal line is used for transmitting a reset signal generated by the host to the slave.

9. The motherboard of claim 1, wherein said master includes a plurality of chip select signal interfaces and a plurality of said slaves; each slave is connected with one chip selection signal interface through one chip selection signal line;

each chip selection signal line is provided with the switch module and the pull-up resistor; the switch module is located between the pull-up resistor and the host.

10. A server, characterized in that it comprises a motherboard according to any of claims 1 to 9.