CN111813731B - Method, device, server and medium for reading memory information - Google Patents
Method, device, server and medium for reading memory information Download PDFInfo
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- CN111813731B CN111813731B CN202010528332.2A CN202010528332A CN111813731B CN 111813731 B CN111813731 B CN 111813731B CN 202010528332 A CN202010528332 A CN 202010528332A CN 111813731 B CN111813731 B CN 111813731B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
Abstract
The application is applicable to the technical field of servers, and provides a method, a device, a server and a medium for reading memory information, wherein the method comprises the following steps: reading memory information of a memory unit through a main module of a Complex Programmable Logic Device (CPLD), and storing the memory information to a register of the CPLD, wherein the register is connected with at least one slave module, and the at least one slave module is respectively connected with target units in one-to-one correspondence; when a memory information reading request from a target unit is received, the memory information in the register is read through a slave module corresponding to the target unit, and the memory information is sent to the target unit. By the method, the target units can read the memory information through the bus at the same time.
Description
Technical Field
The present application relates to the technical field of servers, and in particular, to a method, an apparatus, a server, and a medium for reading memory information.
Background
A Baseboard Management Controller (BMC) monitors a power supply, a temperature, and the like of a system to ensure that the system is in a normal operation state. In the process of monitoring the server, the BMC needs to read memory information, such as a Serial Number (SN) of a memory product, temperature, and the like.
In a home server platform, currently, a Central Processing Unit (CPU) and a BMC read memory information through an Inter-Integrated Circuit (IIC). When the BMC also needs to read memory information, there are cases where two masters access one slave. According to the IIC communication standard, two devices for transmitting data cannot be in a master mode at the same time, namely two devices only having the master mode cannot directly communicate, one device is required to be in the master mode, the other device is in a slave mode, and only one device can transmit data at the same time, namely the master device transmits the data and the slave device receives the data; or the slave device sends data and the master device receives data.
Therefore, both BMC and CPU are IIC masters, and cannot directly read memory Serial Presence Detect (SPD) register information at the same time. At present, the IIC channel can also be switched by using a switch, the memory IIC is selected to be connected with the BMC or the CPU, and only one party can be connected with the memory IIC at the same time, but in the actual use process, the time for switching the channel is strict, because if one device does not finish communication, the channel is switched to another device, and the phenomenon that the memory IIC is hung up easily occurs.
Disclosure of Invention
The embodiment of the application provides a method, a device, a server and a medium for reading memory information, which can solve the problem that a substrate management controller and a central processing unit cannot read the memory information through an IIC bus at the same time.
In a first aspect, an embodiment of the present application provides a method for reading memory information, which is applied to a server, where the server includes a complex programmable logic device CPLD, and the method includes:
reading memory information of a memory unit through a main module of the CPLD, and storing the memory information to a register of the CPLD, wherein the register is connected with at least one slave module, and the at least one slave module is respectively connected with target units in one-to-one correspondence;
when a memory information reading request from a target unit is received, the memory information in the register is read through a slave module corresponding to the target unit, and the memory information is sent to the target unit.
In a second aspect, an embodiment of the present application provides an apparatus for reading memory information, which is applied to a server, where the server includes a complex programmable logic device CPLD, and the apparatus includes:
the memory information reading module is used for reading the memory information of the memory unit through the main module of the CPLD and storing the memory information to the register of the CPLD, the register is connected with at least one slave module, and the at least one slave module is respectively connected with the target units which correspond to one another one by one;
and the memory information sending module is used for reading the memory information in the register through the slave module corresponding to the target unit and sending the memory information to the target unit when receiving a memory information reading request from the target unit.
In a third aspect, an embodiment of the present application provides a server, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the method of the first aspect when executing the computer program.
In a fourth aspect, the present application provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the computer program implements the method of the first aspect.
In a fifth aspect, embodiments of the present application provide a computer program product, which, when run on a server, causes the server to perform the method described in the first aspect.
Compared with the prior art, the embodiment of the application has the beneficial effects that: in the embodiment of the application, a master module and a plurality of slave modules are established in a CPLD, the master module and the slave modules are both connected with a register inside the CPLD, the master module is connected with an external memory unit, and the slave modules are respectively and correspondingly connected with a target unit which needs to read memory information; reading memory information from a memory unit through a main module of the CPLD, and then storing the memory information in a register; and the target unit reads the memory information from the register through the slave module correspondingly connected. According to the embodiment of the application, the memory information can be read, stored and sent by using the CPLD, so that each target unit can read the memory information at any time through the connected slave module, and conflicts can not occur when a plurality of target units access the memory information at the same time.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic flowchart illustrating a method for reading memory information according to an embodiment of the present disclosure;
fig. 2 is a schematic flowchart illustrating a method for reading memory information according to a second embodiment of the present application;
fig. 3 is a schematic flowchart of a method for reading memory information according to a third embodiment of the present application;
fig. 4 is a schematic structural diagram of a memory information reading apparatus according to a fourth embodiment of the present application;
fig. 5 is a schematic structural diagram of a memory information reading apparatus according to a fifth embodiment of the present application;
FIG. 6 is a schematic diagram of sequential logic control provided in accordance with an embodiment of the present application;
fig. 7 is a schematic structural diagram of a server according to a sixth embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".
Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing a relative importance or importance.
Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.
Fig. 1 is a schematic flowchart of a method for reading memory information according to an embodiment of the present application, where as shown in fig. 1, the method includes:
s101, reading memory information of a memory unit through a main module of the CPLD, and storing the memory information to a register of the CPLD, wherein the register is connected with at least one slave module, and the at least one slave module is respectively connected with target units in one-to-one correspondence;
the method of the embodiment can be applied to a server. These servers are typically servers using a domestic platform, such as the Feiteng platform. In the X86 platform, the cpu reads the SPD register information of the memory bank through an Integrated Circuit (IC) and internally analyzes the SPD register information, but in the soar platform, the cpu cannot analyze the SPD register information and reads the memory information through an IIC bus. According to the IIC communication protocol, only one master device can use the IIC bus at a time, and thus two devices cannot read memory information through the IIC bus at the same time.
In the embodiment, one CPLD is used, and the CPLD simulates and establishes a main IIC device and a plurality of slave IIC devices through simulating an IIC time sequence. The master module is a master IIC device simulated by the CPLD, and the slave module is a slave IIC device simulated by the CPLD. The CPLD may further include registers respectively connected to the master module and the slave modules.
The memory information may be information stored in a memory SPD register, such as a memory product serial number, a temperature, and the like. The main module has the use right of an IIC bus connected with the memory, can read memory information through a memory address, receives the memory information through the IIC bus, and then stores the memory information in a register of the CPLD.
S102, when a memory information reading request from a target unit is received, the memory information in the register is read through a slave module corresponding to the target unit, and the memory information is sent to the target unit.
Specifically, the target unit is a unit that needs to read memory information, for example, in a power-on self-test process, the central processing unit needs to access the memory SPD register to obtain the memory information to start the computer; the baseboard management controller needs to read memory information in real time to ensure the normal operation of the server.
Specifically, a target unit may be correspondingly connected to a slave module, and when the target unit needs to read memory information, a memory information reading instruction may be sent to the slave module, and then the slave module receives the instruction and reads the memory information from the register and sends the memory information to the target unit.
In a possible implementation manner, each target unit can be respectively connected with the register of the CPLD through an IIC bus, and one target unit has the right of use of the IIC bus connected with the register and stores the address of the register; when the memory information needs to be read, the target unit reads the memory information in the register through the IIC bus and the register address, and then receives the memory information through the IIC bus.
In this embodiment, a master module and at least one slave module are created in the CPLD, and the master module can read memory information and store the read memory information in a register; the target unit needing to read the memory information can read the memory information from the register through the slave module without directly reading the information from the memory, so that a plurality of devices can read the memory information through the IIC at the same time.
Fig. 2 is a schematic flowchart of a method for reading memory information according to a second embodiment of the present application, where as shown in fig. 2, the method includes:
s201, reading the memory information of a memory unit through the main module at preset time intervals, and storing the memory information into a register of the CPLD;
the embodiment can be applied to a server, and the server can use a Feiteng server platform.
Specifically, a master module and a plurality of slave modules are created in the CPLD by using the CPLD as a transition unit for reading the memory information. The main module is connected with the memory through the IIC bus, and sends an address and an instruction for reading memory information through the IIC bus, and then receives the memory information sent by the memory through the IIC bus and stores the memory information in the register.
S202, when a memory information reading request from a central processing unit is received, the memory information stored in the register is read through the first slave module, and the memory information is sent to the central processing unit;
specifically, in the power-on self-test process, the central processing unit needs to access the memory SPD information to start the computer, so that when the central processing unit is started, the memory information can be read from the register through the connected first slave module for the power-on self-test.
When the first slave module receives a memory information reading request from the central processing unit, the memory information can be read from the connected register and then sent to the central processing unit through the IIC bus.
And S203, when a memory information reading request from the baseboard management controller is received, reading the memory information stored in the register through the second slave module, and sending the memory information to the baseboard management controller.
Specifically, the baseboard management controller can remotely monitor and manage the server, and in the monitoring process of the server, the memory information needs to be read at any time, for example, the memory temperature needs to be checked at any time. The baseboard management controller ensures that the system is in a normal operation state by monitoring the power supply, the temperature and the like of the server.
The baseboard management controller can be connected with the second slave module, and then the memory information is read from the register through the second slave module. The main module can read the memory information at preset time intervals and store the memory information in the register, so the baseboard management controller can read the memory information at any time.
In the embodiment of the application, both the baseboard management controller and the central processing unit can read the memory information from the register of the CPLD through the connected slave module, thereby avoiding the conflict when the baseboard management controller and the central processing unit directly read the information from the memory SPD register through the IIC bus.
Fig. 3 is a schematic flowchart of a method for reading memory information according to a third embodiment of the present application, where as shown in fig. 3, the method includes:
s301, when the server is started, controlling the memory unit to be powered on and controlling the central processing unit to be in a power-off state;
specifically, when the server is connected to the power supply, the baseboard management controller and the CPLD are in a constantly powered-on operating state in the server, and the baseboard management controller and the CPLD start to operate as long as external power is supplied.
In the power-on self-test process, the central processing unit needs to read the memory information from the memory unit, so that the memory unit can be controlled to be powered on firstly, and the central processing unit is not powered on firstly.
S302, after the memory information of the memory unit is read through the main module and stored in the register of the CPLD, the CPU is controlled to be powered on;
specifically, after the memory is powered on, the CPLD obtains the memory information from the SPD register of the memory through the master module, and then stores the memory information in the register of the CPLD. Generally, the address of the memory SPD register is fixed, so the master module can directly send the address to be accessed and the command related to the reading of the memory information through the IIC bus; and then the transmitted memory information is received through the IIC bus, and the memory information is stored in a register of the CPLD.
S303, when a memory information reading request from a central processing unit is received, reading the memory information stored in the register through the first slave module, and sending the memory information to the central processing unit;
s304, when a memory information reading request from a substrate management controller is received, reading the memory information stored in the register through the second slave module, and sending the memory information to the substrate management controller;
s303 to S304 in this embodiment are similar to S202 to S203 in the above embodiments, and may refer to each other, which are not described herein again.
S305, reading clock information of a clock chip through a main module of the CPLD, and storing the clock information to a register of the CPLD;
a CPLD module is adopted as a transition unit for reading the clock information of a clock chip, so that the clock information can be simultaneously read by a plurality of target units. Specifically, one master module and a plurality of slave modules can be created in the CPLD module; the master module can be connected with the clock chip through an IIC bus, and the slave modules can be respectively connected with a target unit needing to read clock information; the CPLD comprises a register, and the master module and each slave module are connected with the register.
The main module of the CPLD can read the clock information of the clock chip through the IIC bus and store the clock information in the connected register.
S306, when a clock information reading request from a target unit is received, reading the clock information in the register through a slave module corresponding to the target unit, and sending the clock information to the target unit.
The target unit may include a baseboard management controller and a central processor.
Specifically, each target unit is respectively connected with the slave module through an IIC bus, when clock information needs to be read, the target unit sends a clock information reading request to the connected slave module through the IIC bus, and after the slave module receives the clock information reading request, the clock information is read from the register and sent to the target unit through the IIC bus.
In the embodiment, the CPLD module is used for controlling the power-on time sequence, the central processing unit is powered on after the memory is powered on and the memory information is read, the condition that the memory is not powered on when the central processing unit reads the memory information is avoided, and the CPLD is used for controlling the time sequence, so that the debugging difficulty of software is reduced; in addition, the CPLD module can be used for enabling different target units to simultaneously read the clock information of the clock chip; and each target unit can acquire information in parallel through the IIC bus without mutual interference.
Fig. 4 is a schematic structural diagram of a memory information reading apparatus 4 according to a fourth embodiment of the present application, and as shown in fig. 4, the apparatus 4 includes:
a memory information reading module 41, configured to read memory information of a memory unit through a master module of the CPLD, and store the memory information in a register of the CPLD, where the register is connected to at least one slave module, and the at least one slave module is connected to one-to-one corresponding target unit;
and a memory information sending module 42, configured to, when receiving a memory information reading request from a target unit, read the memory information in the register through a slave module corresponding to the target unit, and send the memory information to the target unit.
The memory information reading module 41 includes:
and the reading submodule is used for reading the memory information of the memory unit through the main module at preset time intervals and storing the memory information into the register of the CPLD.
In the above apparatus, the target unit includes a central processing unit of the server, the at least one slave module includes a first slave module respectively connected to the register and the central processing unit, and the memory information sending module 42 includes:
and the first memory information sending submodule is used for reading the memory information stored in the register through the first slave module and sending the memory information to the central processing unit when receiving a memory information reading request from the central processing unit.
In the above apparatus, the target unit includes a baseboard management controller of the server, the at least one slave module includes a second slave module respectively connected to the register and the baseboard management controller, and the memory information sending module 42 further includes:
and the second memory information sending submodule is used for reading the memory information stored in the register through the second slave module and sending the memory information to the substrate management controller when a memory information reading request from the substrate management controller is received.
The above device 4 further comprises:
the memory power-on control module is used for controlling the power-on of the memory unit and controlling the central processing unit to be in a power-off state when the server is started;
and the central processing unit electrification control module is used for controlling the central processing unit to be electrified after the main module reads the memory information of the memory unit and stores the memory information into the register of the CPLD.
The above-mentioned device 4 further comprises:
the clock information reading module is used for reading the clock information of a clock chip through the main module of the CPLD and storing the clock information into the register of the CPLD,
and the clock information sending module is used for reading the clock information in the register through the slave module corresponding to the target unit and sending the clock information to the target unit when receiving a clock information reading request from the target unit.
Fig. 5 is a schematic structural diagram of a memory information reading device according to a fifth embodiment of the present application, and as shown in fig. 5, the device includes a CPLD module, where the CPLD module includes a master IIC module and two slave IIC modules; the master IIC module and the slave IIC module are both connected to the register. The main IIC module is connected with the memory SPD register through an IIC bus, and the two slave modules are respectively connected with the substrate management controller BMC and the central processing unit CPU through the IIC bus. The CPLD can perform timing control, and fig. 6 is a timing logic control diagram of the CPLD.
When the computer is started, the CPLD controls the memory to be powered on, then a main module of the CPLD reads the memory information in the memory SPD register through the IIC bus, and then the read memory information is stored in the register; and then the CPLD controls the central processing unit to be electrified, the central processing unit can send a memory information reading instruction through the IIC bus in the power-on self-test process, when a slave module connected with the central processing unit receives the memory information reading instruction from the central processing unit, the memory information is read from the register, and then the memory information is sent to the central processing unit through the IIC bus. The central processing unit adopts the received memory information to complete the power-on self-test process.
And under the condition that the server is connected with a power supply, the CPLD and the baseboard management controller are both in a power-on state. The baseboard management controller reads the memory information for monitoring the operation state of the server, and generally needs to acquire the memory information at any time. The master module in the COLD can read the memory information at preset time intervals and then store the memory information in the register, and when the slave module connected with the substrate management controller receives a memory information reading request from the substrate management controller, the slave module acquires the latest read memory information from the register and sends the memory information to the substrate management controller through the IIC bus.
In addition, the structure of the CPLD in fig. 5 can also be used in other information reading scenarios. For example, the master module of the CPLD may be connected to the clock system chip, and the two slave modules are connected to the central processor and the baseboard management controller, respectively, so that the central processor and the baseboard management controller can read the clock information of the clock chip at any time through the CPLD, and when the information is read at the same time, no conflict occurs.
Fig. 7 is a schematic structural diagram of a server according to a sixth embodiment of the present application. As shown in fig. 7, the server 7 of this embodiment includes: at least one processor 70 (only one shown in fig. 7), a memory 71, and a computer program 72 stored in the memory 71 and executable on the at least one processor 70, the processor 70 implementing the steps of any of the various method embodiments described above when executing the computer program 72.
The server 7 may include, but is not limited to, a processor 70, a memory 71. Those skilled in the art will appreciate that fig. 7 is merely an example of the server 7, and does not constitute a limitation of the server 7, and may include more or less components than those shown, or combine certain components, or different components, such as input output devices, network access devices, etc.
The processor 70 may be a Central Processing Unit (CPU), and the processor 70 may be other general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 71 may in some embodiments be an internal storage unit of the server 7, such as a hard disk or a memory of the server 7. The memory 71 may also be an external storage device of the server 7 in other embodiments, such as a plug-in hard disk provided on the server 7, a Smart Media Card (SMC), a Secure Digital (SD) card, a flash memory card (FlashCard), and the like. Further, the memory 71 may also include both an internal storage unit and an external storage device of the server 7. The memory 71 is used for storing an operating system, an application program, a BootLoader (BootLoader), data, and other programs, such as program codes of the computer programs. The memory 71 may also be used to temporarily store data that has been output or is to be output.
It should be noted that, for the information interaction, execution process, and other contents between the above-mentioned devices/units, the specific functions and technical effects thereof are based on the same concept as those of the embodiment of the method of the present application, and specific reference may be made to the part of the embodiment of the method, which is not described herein again.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. For the specific working processes of the units and modules in the system, reference may be made to the corresponding processes in the foregoing method embodiments, which are not described herein again.
An embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the computer program implements the steps in the foregoing method embodiments.
The embodiments of the present application provide a computer program product, which when executed on a server, enables the server to implement the steps in the above method embodiments.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, all or part of the processes in the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium and can implement the steps of the embodiments of the methods described above when the computer program is executed by a processor. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer readable medium may include at least: any entity or device capable of carrying computer program code to a photographing device/server, a recording medium, computer memory, read-only memory (ROM), random-access memory (RAM), an electrical carrier signal, a telecommunications signal, and a software distribution medium. Such as a usb-drive, a removable hard drive, a magnetic or optical disk, etc. In certain jurisdictions, computer-readable media may not be an electrical carrier signal or a telecommunications signal in accordance with legislative and patent practice.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus/server and method may be implemented in other ways. For example, the above-described apparatus/server embodiments are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (9)
1. A method for reading memory information is applied to a server, wherein the server comprises a Complex Programmable Logic Device (CPLD), and the method comprises the following steps:
reading memory information of a memory unit through a main module of the CPLD, and storing the memory information to a register of the CPLD, wherein the register is connected with a plurality of slave modules which are respectively connected with target units in one-to-one correspondence; the CPLD simulates and builds a main IIC device and a plurality of slave IIC devices through simulating an IIC time sequence, the main module is the CPLD simulated main IIC device, the slave modules are the CPLD simulated slave IIC devices, and the CPLD further comprises registers respectively connected with the main module and each slave module;
when a memory information reading request from a target unit is received, reading the memory information in the register through a slave module corresponding to the target unit, and sending the memory information to the target unit; each target unit is respectively connected with the register of the CPLD through an IIC bus, has the use right of the IIC bus connected with the register and stores the address of the register;
the target unit comprises a central processor of the server;
before the memory information of the memory unit is read by the main module of the CPLD, the method further includes:
when the server is started, controlling the memory unit to be powered on and controlling the central processing unit to be in a power-off state;
and after the main module reads the memory information of the memory unit and stores the memory information into the register of the CPLD, the CPU is controlled to be powered on.
2. The method of claim 1, wherein reading memory information of a memory unit by a primary module of the CPLD and storing the memory information to a register of the CPLD comprises:
and reading the memory information of the memory unit through the main module at preset time intervals, and storing the memory information into a register of the CPLD.
3. The method as claimed in claim 1 or 2, wherein the plurality of slave modules include a first slave module respectively connected to the register and the central processing unit, and when receiving a memory information reading request from a target unit, the reading the memory information in the register by the slave module corresponding to the target unit and sending the memory information to the target unit includes:
when a memory information reading request from a central processing unit is received, the memory information stored in the register is read through the first slave module, and the memory information is sent to the central processing unit.
4. The method of claim 3, wherein the target unit comprises a baseboard management controller of the server, the plurality of slave modules comprises second slave modules respectively connected to the register and the baseboard management controller, and when receiving a memory information read request from a target unit, the reading of the memory information in the register by the slave module corresponding to the target unit and the sending of the memory information to the target unit comprises:
and when a memory information reading request from a substrate management controller is received, reading the memory information stored in the register through the second slave module, and sending the memory information to the substrate management controller.
5. The method of claim 4, wherein reading the memory information stored in the register by the first slave module is performed in parallel with reading the memory information stored in the register by the second slave module.
6. The method of claim 1, further comprising:
reading clock information of a clock chip through a main module of the CPLD, and storing the clock information into a register of the CPLD;
when a clock information reading request from a target unit is received, the clock information in the register is read through a slave module corresponding to the target unit, and the clock information is sent to the target unit.
7. The device for reading the memory information is applied to a server, wherein the server comprises a Complex Programmable Logic Device (CPLD), and the device comprises:
the memory information reading module is used for reading the memory information of a memory unit through a main module of the CPLD and storing the memory information to a register of the CPLD, the register is connected with a plurality of slave modules, and the slave modules are respectively connected with target units which correspond to one another one by one; the CPLD simulates and builds a main IIC device and a plurality of slave IIC devices through simulating an IIC time sequence, the main module is the CPLD simulated main IIC device, the slave modules are the CPLD simulated slave IIC devices, and the CPLD further comprises registers respectively connected with the main module and each slave module;
the memory information sending module is used for reading the memory information in the register through a slave module corresponding to the target unit and sending the memory information to the target unit when receiving a memory information reading request from the target unit; each target unit is respectively connected with the register of the CPLD through an IIC bus, and has the use right of the IIC bus connected with the register and stores the address of the register;
the target unit comprises a central processor of the server;
the device, still include:
the memory power-on control module is used for controlling the power-on of the memory unit and controlling the central processing unit to be in a power-off state when the server is started;
and the central processing unit power-on control module is used for controlling the central processing unit to be powered on after the main module reads the memory information of the memory unit and stores the memory information into the register of the CPLD.
8. A server comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the method according to any of claims 1 to 6 when executing the computer program.
9. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1 to 6.
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| CN112667483B (en) * | 2021-01-04 | 2023-03-28 | 上海兆芯集成电路有限公司 | Memory information reading device and method for server mainboard and server |
| CN112965930B (en) * | 2021-05-18 | 2021-08-31 | 中科可控信息产业有限公司 | Access controller, access control method, computer device, and readable storage medium |
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