JPS5616223A - Interface circuit - Google Patents

Interface circuit

Info

Publication number
JPS5616223A
JPS5616223A JP9159779A JP9159779A JPS5616223A JP S5616223 A JPS5616223 A JP S5616223A JP 9159779 A JP9159779 A JP 9159779A JP 9159779 A JP9159779 A JP 9159779A JP S5616223 A JPS5616223 A JP S5616223A
Authority
JP
Japan
Prior art keywords
level
trailing
leading
circuit
cpu12
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9159779A
Other languages
Japanese (ja)
Inventor
Katsuhiro Tsuchida
Shinichiro Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9159779A priority Critical patent/JPS5616223A/en
Publication of JPS5616223A publication Critical patent/JPS5616223A/en
Pending legal-status Critical Current

Links

Landscapes

  • Logic Circuits (AREA)
  • Dc Digital Transmission (AREA)
  • Power Sources (AREA)
  • Direct Current Feeding And Distribution (AREA)

Abstract

PURPOSE: To realize the information system of high quality, by avoiding the production of unnecessary pulse noise and the period of unstable state at leading and trailing of DC level, at the connection between CPU and external circuits.
CONSTITUTION: The normally opened relay contact 32 is placed in series connection with the signal line for CPU12 and external circuit 13. This contact 32 is switched with the relay driving circuit 33, and this circuit 33 has the transistor TR34 and the relay coil 35. Further, at the collector side of TR34, DC level V1 is given and at the base side of TR34, the DC level V2 is fed, the leading of the level V2 is delayed for a given time than the leading of the level V1, and the trailing of the level V2 is ahead the trailing of the level V1. Further, the level V1 can be the level of the supply power 15 to the logic circuit of CPU12. Thus, at the leading and trailing of the DC level, the production of unstable operation period and unnecessary pulse noise is avoided to realize the information system of high quality.
COPYRIGHT: (C)1981,JPO&Japio
JP9159779A 1979-07-20 1979-07-20 Interface circuit Pending JPS5616223A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9159779A JPS5616223A (en) 1979-07-20 1979-07-20 Interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9159779A JPS5616223A (en) 1979-07-20 1979-07-20 Interface circuit

Publications (1)

Publication Number Publication Date
JPS5616223A true JPS5616223A (en) 1981-02-17

Family

ID=14030956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9159779A Pending JPS5616223A (en) 1979-07-20 1979-07-20 Interface circuit

Country Status (1)

Country Link
JP (1) JPS5616223A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57156930U (en) * 1981-03-27 1982-10-02
JPS5827218A (en) * 1981-08-10 1983-02-17 Nec Corp Generating circuit of power supply decision signal for logical unit
JPS5954354A (en) * 1982-09-22 1984-03-29 Fujitsu Ltd Signal transmitting method
CN102098038A (en) * 2010-11-23 2011-06-15 中国人民解放军63961部队 Signal conditioning card

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57156930U (en) * 1981-03-27 1982-10-02
JPS5827218A (en) * 1981-08-10 1983-02-17 Nec Corp Generating circuit of power supply decision signal for logical unit
JPH0223886B2 (en) * 1981-08-10 1990-05-25 Nippon Electric Co
JPS5954354A (en) * 1982-09-22 1984-03-29 Fujitsu Ltd Signal transmitting method
CN102098038A (en) * 2010-11-23 2011-06-15 中国人民解放军63961部队 Signal conditioning card

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