JPH01150392A - Erroneous operation preventive circuit in electronic device - Google Patents

Erroneous operation preventive circuit in electronic device

Info

Publication number
JPH01150392A
JPH01150392A JP62310223A JP31022387A JPH01150392A JP H01150392 A JPH01150392 A JP H01150392A JP 62310223 A JP62310223 A JP 62310223A JP 31022387 A JP31022387 A JP 31022387A JP H01150392 A JPH01150392 A JP H01150392A
Authority
JP
Japan
Prior art keywords
unit
circuit
electronic device
output signal
erroneous operation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62310223A
Other languages
Japanese (ja)
Inventor
Michio Takayama
高山 美知男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62310223A priority Critical patent/JPH01150392A/en
Publication of JPH01150392A publication Critical patent/JPH01150392A/en
Pending legal-status Critical Current

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  • Logic Circuits (AREA)
  • Mounting Of Printed Circuit Boards And The Like (AREA)
  • Direct Current Feeding And Distribution (AREA)
  • Control Of Voltage And Current In General (AREA)

Abstract

PURPOSE:To prevent the functional stoppage of an electronic device from occurring in case of inserting and pulling out an unit by a method wherein an erroneous operation preventive circuit C for preventing any erroneous operation during transmitting and receiving signals between units in case of inserting and pulling out the unit in and from the electrode device is made in the unit. CONSTITUTION:Before inserting an unit 30, an enable signal receiving circuit 12 and an output signal control circuit 11 are supplied with power (f) from an outer power supply A. At this time, the unit 30 is not yet inserted into a shelf 20 of the device not to receive the enable signal (c). Consequently, the circuit 12 transmits a data disabling an output signal (b) to the circuit 11. When the output signal (b) is being disabled, the output part of the circuit 11 provides the disabled output signal (b) with high impedance. Next, the unit 30 is inserted into the shelf 20. The signal (b) provided with the high impedance can prevent the device from causing any erroneous operation. Reversely, when the unit 30 is drawn out of the shelf 20, the circuit 11 can be prevented from causing any erroneous operation by connecting the outer power supply A to a power supply integrating circuit 13.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、電子装置の誤動作防止回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a malfunction prevention circuit for electronic devices.

〔従来の技術〕[Conventional technology]

従来、電子装置にユニットの挿抜を行う場合は、通常電
子装置の電源を停止させて行っており、電子装置の機能
の一時停止をして行っていた。しかしながら電子装置の
規模の拡大、機能の多様化等により、この−時停止が許
容されぬものとなり、そこで、従来は、ユニットの電子
装置へ接続するコネクタ部の端子寸法を差別化し、例え
ば、長短二種類の端子にして、電子装置への挿入時に長
い端子が先に挿入し、次に短い端子が挿入するようにし
て段階的にユニットを挿入し接続している。
Conventionally, when a unit is inserted into or removed from an electronic device, the power to the electronic device is usually stopped, and the functions of the electronic device are temporarily stopped. However, due to the expansion of the scale of electronic devices and the diversification of their functions, this temporary stop is no longer acceptable. Therefore, in the past, the terminal dimensions of the connector section that connects to the electronic device of the unit were differentiated, such as long and short. Two types of terminals are used, and when inserting the unit into an electronic device, the long terminal is inserted first, followed by the short terminal, so that the unit is inserted and connected in stages.

〔発明が一解決しようとする問題点〕[Problem that the invention attempts to solve]

上述した従来のユニットの挿抜方法では、電子装置活性
時のユニット挿抜のタイミングの遅早によっては、電源
供給の保証や、ユニット挿抜過渡期の出力信号の状態レ
ベルの保証等に問題があり、必ずしも全ての誤動作を防
止するまでには至らずシステム全体の!1!1構が一時
停止する場合があるという欠点がある。
In the conventional unit insertion/removal method described above, depending on the timing of unit insertion/removal when the electronic device is active, there are problems in guaranteeing the power supply and guaranteeing the state level of the output signal during the transition period of unit insertion/removal. It is not possible to prevent all malfunctions of the entire system! There is a drawback that 1!1 structure may stop temporarily.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の電子装置の誤動作防止回路は、電子装置を構成
する各ユニットにこの各ユニットの動作の実行又は停止
を制御するイネーブル信号を受信するイネーブル信号受
信回路と、前記電子装置から挿抜されない他ユニットへ
の信号出力を前記イネーブル信号を用いて制御する出力
信号制御回路と、前記電子装置の内部電源から供給され
る電力と前記電子装置の外部電源から供給される電力と
の論理和をとり前記ユニットへ電源を供給する電源統合
回路とを有して構成し、前記電子装置から前記ユニット
の挿抜時に前記ユニット間の信号の授受時の誤動作を防
止する。
A malfunction prevention circuit for an electronic device according to the present invention includes an enable signal receiving circuit that receives an enable signal for controlling execution or stopping of the operation of each unit constituting the electronic device, and other units that are not inserted or removed from the electronic device. an output signal control circuit that controls a signal output to the electronic device using the enable signal; and an output signal control circuit that performs a logical sum of power supplied from an internal power source of the electronic device and power supplied from an external power source of the electronic device; and a power integrated circuit for supplying power to the electronic device to prevent malfunctions when signals are exchanged between the units when the unit is inserted or removed from the electronic device.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例を示す回路図、第2国は第1
図に示す本実施例が適用されているユニットが電子装置
のシェルフから挿抜されている状態を示す模式図である
Figure 1 is a circuit diagram showing one embodiment of the present invention;
FIG. 2 is a schematic diagram showing a state in which a unit to which the illustrated embodiment is applied is inserted and removed from a shelf of an electronic device.

第1図において、本実施例の電子装置の誤動作防止回路
1はイネーブル信号Cを受信して論理反転させるインバ
ータ回路からなるイネーブル信号受信回路12と、被制
御出力信号aをイネーブル信号Cの論理反転信号下−に
よって制御して出力信号すを出力する二人力NAND回
路からなる出力信号制御回路11と、外部電源からの外
部電力fと内部電源からの内部電力eとの論理和によっ
て供給電力dを出力する電源統合回路13とを有して構
成している。
In FIG. 1, a malfunction prevention circuit 1 for an electronic device according to the present embodiment includes an enable signal receiving circuit 12 consisting of an inverter circuit that receives an enable signal C and inverts the logic thereof, and a controlled output signal a that is the logic inversion of the enable signal C. An output signal control circuit 11 consisting of a two-person NAND circuit that outputs an output signal S under the control of a signal LOW, and a logical sum of an external power f from an external power source and an internal power e from an internal power source, calculates a supply power d. The power supply integrated circuit 13 outputs the power.

第2図においては、第1図に示した本実施例の誤動作防
止回路1が実装されるユニット30が、電子装置(図示
省略)のシェルフ20から外部電源から電力fの供給を
受けた状態で、挿抜されることを示している。
In FIG. 2, the unit 30 in which the malfunction prevention circuit 1 of the present embodiment shown in FIG. 1 is mounted is receiving power f from an external power source from the shelf 20 of an electronic device (not shown). , indicates that it will be inserted or removed.

次に、本実施例の動作を第1図、第2図を併用して説明
する。
Next, the operation of this embodiment will be explained using FIG. 1 and FIG. 2 together.

電子装置(以下装置と記す)のシェルフ20ヘユニツト
30を挿入する時点およびシェルフ20からユニット3
0を抜き出す時点には、必ず外部電源から電源供給回路
13へ電力fを供給しておく。
At the time of inserting the unit 30 into the shelf 20 of an electronic device (hereinafter referred to as the device) and from the shelf 20 to the unit 3
When extracting 0, power f is always supplied from the external power source to the power supply circuit 13.

外部電源からの電力fは電源統合回路13に送られこれ
を通過し供給電力dとしてユニット30内で消費される
Power f from the external power supply is sent to the power supply integration circuit 13, passes through this, and is consumed within the unit 30 as supplied power d.

次に、先ず、ユニット30挿入前には、外部電源からの
電力fにより、イネーブル信号受信回路12および出力
信号制御回路11に電源供給を行う。
Next, before the unit 30 is inserted, power is supplied to the enable signal receiving circuit 12 and the output signal control circuit 11 using electric power f from an external power source.

ここで、ユニット30は未だ装置のシェルフ20に挿入
されていないので、イネーブル信号Cは受信されていな
い。従って、イネーブル信号受信回路12は、出力信号
制御回路11に対して出力信号すをディスエーブルとす
る情報を送信する。
Here, since the unit 30 has not yet been inserted into the shelf 20 of the device, the enable signal C has not been received. Therefore, the enable signal receiving circuit 12 transmits information to the output signal control circuit 11 to disable the output signal.

出力信号制御回路11の出力部はオーブンコレクタ又は
3ステート等のデバイスを用いてディスエーブル時には
ハイインピーダンスとなるようにする。
The output section of the output signal control circuit 11 is made to have a high impedance when disabled by using a device such as an oven collector or a three-state device.

次に、上記状態にてユニット30をシェルフ20に挿入
する。ユニット30の出力信号すはハイインピーダンス
となっているので装置に対して誤動作をもたらすことは
ない。
Next, the unit 30 is inserted into the shelf 20 in the above state. Since the output signal of the unit 30 is high impedance, it will not cause any malfunction to the device.

ユニット30がシェルフ20に実装された後、装置より
イネーブル信号Cが送られて来るので、これをイネーブ
ル信号受信回路12で受ける。イネーブル信号受信回路
12では、このイネーブル信号Cに従いイネーブル信号
Cを論理反転したイネーブル情報計を出力信号制御回路
11に送信する。出力信号制御回路では、イネーブル情
報石−に従い被制御出力信号aをイネーブルとする。
After the unit 30 is mounted on the shelf 20, an enable signal C is sent from the device, and this is received by the enable signal receiving circuit 12. In accordance with this enable signal C, the enable signal receiving circuit 12 transmits an enable information meter obtained by logically inverting the enable signal C to the output signal control circuit 11. The output signal control circuit enables the controlled output signal a according to the enable information stone.

以後、ユニット30は、他の実装済ユニットとの間で通
常の信号の授受を行うことができる。
Thereafter, the unit 30 can perform normal signal exchange with other mounted units.

又、ユニット30が装置に実装されると、装置の内部電
源から電力eが電源統合回路13に供給されるので、以
後内部電源を用いてユニット30を動作させれば良いの
で、ユニット30と外部電源との接続は外して良い。
Furthermore, when the unit 30 is mounted on the device, power e is supplied from the device's internal power source to the power supply integrated circuit 13. From now on, it is only necessary to operate the unit 30 using the internal power source. You can disconnect it from the power supply.

逆に、ユニット30をシェルフ20から抜き出す場合も
、先ず外部電源を電源統合回路13に接続しておけば、
抜き出す時の過渡期においても電源供給が保証されるこ
とにより出力信号制御回路11が誤動作することはない
Conversely, when removing the unit 30 from the shelf 20, if you first connect the external power supply to the power supply integrated circuit 13,
Since the power supply is guaranteed even during the transitional period of extraction, the output signal control circuit 11 will not malfunction.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、電子装置を構成するユニ
ット内に本発明による誤動作防止回路を実装することに
より、ユニットの挿抜時に電子装置に誤動作を与える要
因が無くなり、電子装置の機能停止をさせず、かつ電子
装置活性時にても誤動作することなく、ユニットの挿抜
を行うことが出来るので、従来起きていたユニットの挿
抜時でのシステム全体の機能の一時停止をなくすること
ができる効果がある。
As explained above, the present invention implements the malfunction prevention circuit according to the present invention in a unit constituting an electronic device, thereby eliminating a factor that causes malfunction of the electronic device when the unit is inserted or removed, thereby preventing the electronic device from stopping functioning. Since the unit can be inserted and removed without malfunction even when the electronic device is activated, it is possible to eliminate the temporary stoppage of the entire system's function when inserting or removing a unit, which conventionally occurred. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す回路図、第2図は第1
図に示す実施例が適用されているユニットが電子装置の
シェルフから挿抜されている状態を示す模式図である。 1・・・誤動作防止回路、11・・・出力信号制御回路
、12・・・イネーブル信号受信回路、13・・・電源
統合回路、20・・・シェルフ、30・・・ユニット。 代理人 弁理士  内 原  音 1鋲り作防止回昆   I L                 J/1°ボカ不
腎弓弔゛1智回34 7′?  ・イ半−′フ′ル仏号づ亡イ吉回ヱ各/3・
・電床程合回路 第 1 図 第 Z 図
Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 2 is a schematic diagram showing a state in which a unit to which the illustrated embodiment is applied is inserted and removed from a shelf of an electronic device. DESCRIPTION OF SYMBOLS 1... Malfunction prevention circuit, 11... Output signal control circuit, 12... Enable signal receiving circuit, 13... Power supply integration circuit, 20... Shelf, 30... Unit. Agent Patent Attorney Uchihara Oto 1 tack production prevention times I L J/1° boka inrenal archery ゛ 1 wisdom times 34 7'?・Ihan-'ful Buddha name zu auspicious times each/3・
・Electrical bed adjustment circuit Figure 1, Figure Z

Claims (1)

【特許請求の範囲】[Claims] 電子装置を構成する各ユニットにこの各ユニットの動作
の実行又は停止を制御するイネーブル信号を受信するイ
ネーブル信号受信回路と、前記電子装置から挿抜されな
い他ユニットへの信号出力を前記イネーブル信号を用い
て制御する出力信号制御回路と、前記電子装置の内部電
源から供給される電力と前記電子装置の外部電源から供
給される電力との論理和をとり前記ユニットへ電源を供
給する電源統合回路とを有して構成し、前記電子装置か
ら前記ユニットの挿抜時に前記ユニット間の信号の授受
時の誤動作を防止することを特徴とする電子装置の誤動
作防止回路。
an enable signal receiving circuit for receiving an enable signal for controlling execution or stopping of the operation of each unit in each unit constituting the electronic device; and using the enable signal to output a signal to other units that are not inserted or removed from the electronic device. an output signal control circuit for controlling the electronic device; and a power supply integration circuit that performs a logical sum of power supplied from an internal power source of the electronic device and power supplied from an external power source of the electronic device and supplies power to the unit. 1. A malfunction prevention circuit for an electronic device, characterized in that the circuit is configured to prevent malfunctions when signals are exchanged between the units when the unit is inserted or removed from the electronic device.
JP62310223A 1987-12-07 1987-12-07 Erroneous operation preventive circuit in electronic device Pending JPH01150392A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62310223A JPH01150392A (en) 1987-12-07 1987-12-07 Erroneous operation preventive circuit in electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62310223A JPH01150392A (en) 1987-12-07 1987-12-07 Erroneous operation preventive circuit in electronic device

Publications (1)

Publication Number Publication Date
JPH01150392A true JPH01150392A (en) 1989-06-13

Family

ID=18002674

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62310223A Pending JPH01150392A (en) 1987-12-07 1987-12-07 Erroneous operation preventive circuit in electronic device

Country Status (1)

Country Link
JP (1) JPH01150392A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8408649B2 (en) 2007-09-10 2013-04-02 Shiroki Corporation Walk-in seat

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8408649B2 (en) 2007-09-10 2013-04-02 Shiroki Corporation Walk-in seat

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