JPH01150394A - Erroneous operation preventive circuit for electronic device - Google Patents

Erroneous operation preventive circuit for electronic device

Info

Publication number
JPH01150394A
JPH01150394A JP62310225A JP31022587A JPH01150394A JP H01150394 A JPH01150394 A JP H01150394A JP 62310225 A JP62310225 A JP 62310225A JP 31022587 A JP31022587 A JP 31022587A JP H01150394 A JPH01150394 A JP H01150394A
Authority
JP
Japan
Prior art keywords
circuit
unit
electronic device
signal
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62310225A
Other languages
Japanese (ja)
Inventor
Michio Takayama
高山 美知男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62310225A priority Critical patent/JPH01150394A/en
Publication of JPH01150394A publication Critical patent/JPH01150394A/en
Pending legal-status Critical Current

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  • Logic Circuits (AREA)
  • Mounting Of Printed Circuit Boards And The Like (AREA)
  • Control Of Voltage And Current In General (AREA)

Abstract

PURPOSE:To prevent the function of an electronic device from being stopped at the time of insertion and pulling-out of units by a method wherein an erroneous operation preventive circuit for preventing an erroneous operation at the time of delivery and receipt of the signal between the units at the time of insertion and pulling-out of the units in and from the device is mounted in the units. CONSTITUTION:A power supply is supplied to an enable signal reception circuit 11 and an input/output signal control circuit 12 by a power (f) from an external power supply (x) before the unit 30 is inserted. Here, as an enable signal (d) is not received, the circuit 12 is set in a reception mode. In this state, when the unit 30 is inserted in a shelf 20, the circuit 12 does not bring an erroneous operation to a device because the circuit 12 is set in the reception mode. When the unit 30 is mounted to the device, a mounting state signal (h) made in a mounting state informing circuit 14 is informed to the device and as the device side transmits a signal (d), the circuit 12 is released from the reception mode and the unit performs a normal delivery and receipt of signal between other mounting finished units and the unit. Reversely, in case the unit 30 is pulled out of the device, the circuit 12 is never operated erroneously if the external power supply is ready-connected to the unit 30.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は電゛子装置の誤動作防止回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a malfunction prevention circuit for electronic devices.

〔従来の技術〕[Conventional technology]

従来、ユニットの挿抜を行う場合は、通常電子装置の電
源を停止させて行っており、電子装置の機能の一時停止
をして行っていた。しかしながら電子装置の規模の拡大
、機能の多様化等により、この−時停止が許容されぬも
のとなり、そこで、従来は、ユニットの電子装置へ接続
するコネクタ部の端子寸法を差別化し、例えば、長短2
種類の端子にして、電子装置への挿入時に長い端子が先
ず接続し、次に短い端子が接続するようにし、段階的に
ユニットを挿入して接続させている。
Conventionally, when inserting or removing a unit, the power to the electronic device has usually been stopped, and the functions of the electronic device have been temporarily stopped. However, due to the expansion of the scale of electronic devices and the diversification of their functions, this temporary stop is no longer acceptable. Therefore, in the past, the terminal dimensions of the connector section that connects to the electronic device of the unit were differentiated, such as long and short. 2
When inserting the unit into an electronic device, the long terminal is connected first, followed by the short terminal, and the unit is inserted and connected in stages.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のユニット挿抜方法では、電子装置活性時
のユニット挿抜のタイミングの遅早によっては、電源供
給の保証や、ユニット挿抜過渡期の出力信号の状態レベ
ルの保証等に問題があり、必ずしも全ての誤動作を防止
するまでには到らず、システム全体の機能が一時停止す
る場合があるという欠点がある。
In the conventional unit insertion/removal method described above, depending on the timing of unit insertion/removal when the electronic device is activated, there are problems in guaranteeing the power supply and guaranteeing the state level of the output signal during the transition period of unit insertion/removal. However, this method does not go so far as to prevent malfunctions of the system, and has the disadvantage that the function of the entire system may be temporarily stopped.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の電子装置の誤動作回路は、電子装置を構成する
各ユニットの実装状態を通知する実装状態通知回路と、
前記実装状態に呼応して前記電子装置から発せられ前記
ユニット動作の実行又は停止を制御する為の前記イネー
ブル信号を受信するイネーブル信号受信回路と、前記電
子装置から挿抜されない他ユニットとの信号入出力を前
記電子装置からの入出力方向制御信号と前記イネーブル
信号とを用いて制御する入出力信号制御回路と、前記電
子装置の内部電源から供給される電力と前記電子装置の
外部電源から供給される電力との論理和をとり前記ユニ
ットへ電源を供給する電源統合回路とを有して構成し、
前記電子装置から前記ユニットの挿抜時の前記電子装置
の誤動作を防止する。
A malfunction circuit for an electronic device according to the present invention includes a mounting state notification circuit that notifies the mounting state of each unit constituting the electronic device;
an enable signal receiving circuit that receives the enable signal issued from the electronic device in response to the mounting state to control execution or stop of the unit operation; and signal input/output between another unit that is not inserted or removed from the electronic device. an input/output signal control circuit that controls the input/output direction control signal from the electronic device using the input/output direction control signal and the enable signal; and an input/output signal control circuit that controls the input/output direction control signal from the electronic device using the input/output direction control signal and the enable signal; and a power supply integrated circuit that performs a logical sum with electric power and supplies power to the unit,
Malfunction of the electronic device is prevented when the unit is inserted into and removed from the electronic device.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例を示す回路図、第2図は第1
図に示す本実施例が適用されているユニットが電子装置
のシェルフから挿抜されている状態を示す模式図である
Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 2 is a schematic diagram showing a state in which a unit to which the illustrated embodiment is applied is inserted and removed from a shelf of an electronic device.

第1図において、本実施例の電子装置の誤動作防止回路
1は、誤動作防止回路1を実装したユニット(図示省略
)からのイネーブル信号dを受信して論理反転させるイ
ンバータ回路からなるイネーブル信号受信回路11と、
イネーブル信号受信回路11からのイネーブル信号dを
論理反転させた信号子とユニットからの入出力方向制御
信号Cとの論理積によって入出力信号a、bのそれぞれ
の入力、出力を制御する入出力信号制御回路12と、ユ
ニットの内部電源からの電力eと外部電源(図示省略)
からの電力fとの論理和によって供給電力gを出力する
電源統合回路13と、供給電力gを受けると実装状態信
号りを出力する実装状態通知回路14とを有して構成し
ている。
In FIG. 1, a malfunction prevention circuit 1 of an electronic device according to the present embodiment is an enable signal receiving circuit comprising an inverter circuit that receives an enable signal d from a unit (not shown) in which the malfunction prevention circuit 1 is mounted and inverts the logic. 11 and
An input/output signal that controls the input and output of the input/output signals a and b by the AND of the signal element obtained by logically inverting the enable signal d from the enable signal receiving circuit 11 and the input/output direction control signal C from the unit. Control circuit 12, power e from the unit's internal power supply, and external power supply (not shown)
The power supply integration circuit 13 outputs the supplied power g by logical sum with the power f from the mounting state, and the mounting state notification circuit 14 outputs the mounting state signal when receiving the supplied power g.

尚、入出力信号制御回路12は、入出力方向制御信号C
とイネーブル信号dの論理反転信号子との論理積をとる
AND回路(以下ANDと記す)124と、AND12
4の出力信号を論理反転させるインバータ回路(以下I
NVと記す)123と、入出力信号aを受信してAND
124の出力信号のゲート信号によって入出力信号aの
反転信号を出力信号すとするゲート回路(以下GATと
記す)122と、入出力信号すを受信してINV123
の出力信号のゲート信号によって入出力信号すの反転信
号を出力信号aとするGAT 121とを有して構成し
ている。
Note that the input/output signal control circuit 12 receives the input/output direction control signal C.
AND circuit (hereinafter referred to as AND) 124 which takes the logical product of the logic inversion signal of the enable signal d, and the AND12
An inverter circuit that logically inverts the output signal of 4 (hereinafter referred to as I
(denoted as NV) 123 and receives the input/output signal a and AND
A gate circuit (hereinafter referred to as GAT) 122 outputs an inverted signal of the input/output signal a by the gate signal of the output signal of the input/output signal a, and an INV123 receives the input/output signal a.
The GAT 121 outputs an inverted signal of the input/output signal S as an output signal a by a gate signal of the output signal of the GAT 121.

第2図においては、本実施例の誤動作防止回路1が実装
されているユニット30が、電子装置(図示省略)のシ
ェルフ20から挿抜されている状態を示している。
FIG. 2 shows a state in which the unit 30 in which the malfunction prevention circuit 1 of this embodiment is mounted is inserted and removed from the shelf 20 of an electronic device (not shown).

次に、本実施例の動作について第1図、第2図を併用し
て説明する。
Next, the operation of this embodiment will be explained using FIG. 1 and FIG. 2 together.

電子装置(以下装置と記す)のシェルフ20へユニット
30を挿入する時点およびシェルフ20からユニット3
0を抜き出す時点には、必ず、外部電源からの電力fを
電源統合回路13に供給しておく。
When the unit 30 is inserted into the shelf 20 of an electronic device (hereinafter referred to as the device) and when the unit 3 is inserted from the shelf 20
When extracting 0, the power f from the external power supply is always supplied to the power supply integrated circuit 13.

外部電源の電力では電源統合口1113に送られこれを
通過してユニット30内で消費される。
The power from the external power supply is sent to the power supply integration port 1113, passes through this port, and is consumed within the unit 30.

先ず、ユニット30挿入前には、外部電源からの電力f
により、イネーブル信号受信回路11および入出力信号
制御回路12に電源供給を行う。
First, before inserting the unit 30, the power f from the external power source is
As a result, power is supplied to the enable signal receiving circuit 11 and the input/output signal control circuit 12.

ここで、ユニット30は未だシェルフ20に挿入されて
いないので、イネーブル信号dは受信されていない、従
って、イネーブル信号受信回路11は入出力信号制御回
路12に対して受信モードになる情報・を送信する。入
出力信号制御回路12ではこの情報に従い、受信モード
に設定する。
Here, since the unit 30 has not yet been inserted into the shelf 20, the enable signal d has not been received. Therefore, the enable signal receiving circuit 11 sends information to the input/output signal control circuit 12 to enter the receiving mode. do. The input/output signal control circuit 12 sets the reception mode according to this information.

次に、上記状態にてユニット30をシェルフ20に挿入
する。ユニット30の入出力信号制御回路12は受信モ
ードになっているので、装置に対して誤動作をもたらす
ことはない。
Next, the unit 30 is inserted into the shelf 20 in the above state. Since the input/output signal control circuit 12 of the unit 30 is in the reception mode, it will not cause any malfunction to the device.

ユニット30が装置に実装されると、先ず、実装状態通
知回路14で作成した実装状態信号りが装置に通知され
、装置側ではこの実装状態信号りに呼応してイネーブル
信号dを送信するので、これをイネーブル信号受信回路
11で受ける。イネーブル信号受信回路11では、この
イネーブル信号dに従いイネーブル信号dの論理反転し
たイネーブル情報部を入出力信号制御回路12に送信す
る。
When the unit 30 is mounted on a device, the mounting state signal created by the mounting state notification circuit 14 is first notified to the device, and the device side transmits an enable signal d in response to this mounting state signal. This is received by the enable signal receiving circuit 11. In accordance with this enable signal d, the enable signal receiving circuit 11 transmits an enable information part obtained by logically inverting the enable signal d to the input/output signal control circuit 12.

入出力信号制御回路12ではイネーブル情報部にて強制
的な受信モードから解放されるので、以後はユニット3
0内の入出力方向制御信号Cに従って信号の方向を定め
、以後本ユニット30は他の実装済ユニットとの間で通
常の信号の授受を行う。
Since the input/output signal control circuit 12 is released from the forced reception mode in the enable information section, the unit 3
The direction of the signal is determined according to the input/output direction control signal C in 0, and thereafter this unit 30 performs normal signal exchange with other mounted units.

又ユニット30が装置に実装されると、装置の内部電源
が電力eを電源統合回路13に供給するので、以後内部
電源を用いてユニット30を動作させれば良いので、ユ
ニット30と外部電源との接続は外して良い。
Furthermore, when the unit 30 is mounted on the device, the internal power supply of the device supplies power e to the power supply integrated circuit 13, so from now on, it is only necessary to operate the unit 30 using the internal power supply. You can disconnect it.

逆に、ユニット30を装置より抜き出す場合も、先ず外
部電源をユニット30に接続しておけば、抜き出す時の
過渡期においても電源供給が保証されることにより入出
力信号制御回路12が誤動作することはない。
Conversely, when the unit 30 is removed from the device, if the external power supply is connected to the unit 30 first, power supply is guaranteed even during the transition period when the unit 30 is removed, thereby preventing the input/output signal control circuit 12 from malfunctioning. There isn't.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、電子装置を構成するユニ
ット内に本発明による誤動作防止回路を実装することに
より、ユニットの挿抜時に電子装置に誤動作を与える要
因が無くなり、電子装置の機能停止をせず、かつ電子装
置活性時にても誤動作することなく、ユニットの挿抜を
行うことが出来て、特に、実装状態通知回路からのユニ
ットへの電力供給状態であることを示す実装状態信号に
よって確実にイネーブル信号を出力させるので、従来起
きていたユニットの挿抜時でのシステム全体の機能の一
時停止をなくすることができる効果がある。
As explained above, by implementing the malfunction prevention circuit according to the present invention in a unit constituting an electronic device, the cause of malfunction of the electronic device when the unit is inserted or removed is eliminated, and the function of the electronic device is prevented. It is possible to insert and remove the unit without malfunction even when the electronic device is active, and in particular, it is reliably enabled by the mounting status signal from the mounting status notification circuit that indicates that power is being supplied to the unit. Since the signal is output, it is possible to eliminate the temporary suspension of the function of the entire system when a unit is inserted or removed, which conventionally occurs.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す回路図、第2図は第1
図に示す本実施例が適用されているユニットが電子装置
のシェルフから挿抜されている状態を示す模式図である
。 1・・・誤動作防止回路、11・・・イネーブル信号受
信回路、12・・・入出力信号制御回路、13・・・電
源統合回路、14・・・実装状態通知回路、121,1
22・・・ゲート回路(GAT) 、123・・・イン
バータ回路(INV)、124・・・AND回路(AN
D)。 代理人 弁理士  内 原  音 第1図
Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 2 is a schematic diagram showing a state in which a unit to which the illustrated embodiment is applied is inserted and removed from a shelf of an electronic device. DESCRIPTION OF SYMBOLS 1... Malfunction prevention circuit, 11... Enable signal receiving circuit, 12... Input/output signal control circuit, 13... Power supply integration circuit, 14... Mounting status notification circuit, 121,1
22... Gate circuit (GAT), 123... Inverter circuit (INV), 124... AND circuit (AN
D). Agent Patent Attorney Oto Uchihara Figure 1

Claims (1)

【特許請求の範囲】[Claims]  電子装置を構成する各ユニットの実装状態を通知する
実装状態通知回路と、前記実装状態に呼応して前記電子
装置から発せられ前記ユニットの動作の実行又は停止を
制御するイネーブル信号を受信するイネーブル信号受信
回路と、前記電子装置から挿抜されない他ユニットとの
信号入出力を前記電子装置からの入出力方向制御信号と
前記イネーブル信号とを用いて制御する入出力信号制御
回路と、前記電子装置の内部電源から供給される電力と
前記電子装置の外部電源から供給される電力との論理和
をとり前記ユニットへ電源を供給する電源統合回路とを
有して構成し、前記電子装置から前記ユニットの挿抜時
の前記電子装置の誤動作を防止することを特徴とする電
子装置の誤動作防止回路。
a mounting state notification circuit that notifies the mounting state of each unit constituting the electronic device; and an enable signal that receives an enable signal issued from the electronic device in response to the mounting state and controlling execution or stop of the operation of the unit. an input/output signal control circuit that controls signal input/output between a receiving circuit and other units that are not inserted or removed from the electronic device using an input/output direction control signal from the electronic device and the enable signal; and a power supply integration circuit that performs a logical OR of the power supplied from the power supply and the power supplied from the external power supply of the electronic device and supplies the power to the unit, and the unit is inserted and removed from the electronic device. A malfunction prevention circuit for an electronic device, characterized in that the circuit prevents malfunction of the electronic device when the electronic device is malfunctioned.
JP62310225A 1987-12-07 1987-12-07 Erroneous operation preventive circuit for electronic device Pending JPH01150394A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62310225A JPH01150394A (en) 1987-12-07 1987-12-07 Erroneous operation preventive circuit for electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62310225A JPH01150394A (en) 1987-12-07 1987-12-07 Erroneous operation preventive circuit for electronic device

Publications (1)

Publication Number Publication Date
JPH01150394A true JPH01150394A (en) 1989-06-13

Family

ID=18002696

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62310225A Pending JPH01150394A (en) 1987-12-07 1987-12-07 Erroneous operation preventive circuit for electronic device

Country Status (1)

Country Link
JP (1) JPH01150394A (en)

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