JPS61133462A - Bus controlling device - Google Patents

Abstract

PURPOSE:To improve the reliability of the entire system by constituting the titled device with a bus buffer, a change point detection part detecting a change point of a voltage level of a local data bus, a system data bus and a buffer control part inhibiting the control of a central processing unit to the connection of the local data bus. CONSTITUTION:A system data bus 102 is connected to a data input/output port of a CPU. A peripheral device 110 is accessed by the CPU. A local data bus 121 is connected to a data output port of the peripheral device. A bus buffer 122 connects the system data bus and the local data bus and amplifies a data signal. A change point detection part 123 detects a voltage level fluctuation of a level giving effect on the system data bus on the local data bus and outputs a change point detection signal TRG. A buffer control part 124 receives a PRD signal generated from a decoder, and when a specified time is elapsed after the change point detection part receives the TRG signal, the part 124 gives a connection signal GATE between the system data bus and the local data bus to the bus buffer.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a system data bus connected to a data output port of a central processing unit (hereinafter abbreviated as cpu) and the output of a peripheral device accessed by the above-mentioned GPTI. The present invention relates to a bus control device that controls the connection of a local data bus connected to a port.

BACKGROUND OF THE INVENTION In recent years, with the spread of microcomputers, a large number of peripheral devices are often connected to the microcomputers to increase versatility and processing power. When transferring data between the CPU on a microcomputer and a peripheral device, a system data bus connected to the data input/output port of the CPH and a local data bus connected to the data input/output port of the peripheral device are connected. A data communication path is formed by connecting via a path buffer for data signal amplification, and the CPU
specifies the peripheral device using an address, and controls data transfer to the peripheral device using various control signals.

An example of a control procedure when data is received from a peripheral device accessed by the conventional CPU described above will be described below with reference to the drawings.

FIG. 4 is a block diagram showing the connection state between a conventional CPU and peripheral devices. In FIG. 4, 400 is the central processing unit C
It is PU. 401 is a system control bus through which the CPU outputs various control signals, and 402 is a system address bus through which the CPU outputs an address signal DH. 403 is a system data bus connected to the data output port of the CPU. 41Q is the above CP
This is a peripheral device accessed by H. 411 is a local data bus connected to the data output port of the peripheral device. A bus buffer 412 connects the system data bus to the mechanical data bus and amplifies data signals. , 413c, decode the data read signal RD on the system control bus and the node read signal DH on the system address bus to generate a connection instruction signal GATE between the system data bus and the local data bus for the path buffer; It is also a decoder that generates the peripheral device selection signal SEL and the data read signal PRD.

In the connection state between the CPU and the peripheral device configured as above, the procedure and operation of each part when receiving and receiving data from the peripheral device accessed by the CPU will be described below with reference to the timing diagram shown in FIG. I will explain. First, the CPU 400q outputs a DR signal to the system address bus 402 to instruct the peripheral device 410 to be accessed. The busy decoder 412 decodes the DR signal on the system address bus 402 and sends the signal to the peripheral device 410.
The L signal is provided to enable control over the peripheral device 410.

Next, the CPU 4oo outputs the data read signal RD to the system control bus 401 and outputs the data read signal RD to the decoder +13tt.
The HD double signal is received from the i system control bus 401 and sent to the system data bus 4 to the path buffer 412.
Connection instruction signal Gm τ between o3 and local data bus 411
E and data read signal P for one peripheral device 410
Output RD. Next, the peripheral device 410 outputs the data signal DATA2 to the data output port connected to the local data bus 411 after an access time Tm has elapsed since receiving the PRD signal. Next, the DAT 2 output from the data output port of the peripheral device 410 passes through the local data bus 411 and is amplified by the path buffer 412.
The DAT1 signal becomes the ATA1 signal and reaches the data output port of the CPU 400 through the 7-stem data bus 403. Next, cptzoo connects the system data bus 40 to the system data bus 40 at the rising timing when the RD double signal output ends.
It receives DATAI from the input/output port connected to 3 and finishes the data reading operation.

Problems to be Solved by the Invention However, in the above configuration, the voltage level on the local data bus, which is in a high impedance state before the peripheral device outputs data, is affected by fluctuations in the power supply voltage and GND level. Fluctuations occur due to the influence of external noise. As shown in FIG. 6, this fluctuation occurs on the system data bus as noise having a sufficient signal level due to the amplification effect of the bidirectional buffer. For this reason,
This has a problem in that it has an adverse effect such as crosstalk on a large number of signal lines in the vicinity of the system data bus, and is likely to cause malfunctions of the system including the GPU and peripheral devices.

In view of the above problems, the present invention provides data bus control that prevents voltage level fluctuations occurring on the local data bus in a high impedance state from appearing as noise on the system data bus, and improves the reliability of system operation. It provides equipment.

Means for Solving the Problems In order to solve the above problems, the data bus control device of the present invention includes: (c) a connection between the system data bus and the local data bus, and a data signal sent from the local data bus to the system data bus. a path buffer for amplifying the voltage level of the local data bus; a change point detection section for detecting a change point in the voltage level of the local data bus; and a change point detection section for detecting a change point in the voltage level of the local data bus;
The buffer control unit prohibits the central processing unit from controlling the connection between the system data bus and the local data bus.

According to the above-described structure, the present invention detects voltage level fluctuations when the local data bus is in a high impedance state and prohibits connection between the system data bus and the local data bus, thereby preventing failure of the local data bus. To eliminate the cause of system malfunction and improve the reliability of the entire system by preventing noise generation on the system data bus due to a stable state and preventing the influence on many signal lines near the system data bus. becomes.

Embodiment Hereinafter, a bus control device according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a bus control device and its connection state in an embodiment of the present invention. In Figure 1, 1
00 is the stem control bus where the CPU outputs various control signals, 101 is the address signal DR where the CPU outputs various control signals.
A system address bus 102 is a system data bus connected to the data input/output port of the CPU. 110 is a peripheral device accessed by the CPU;
121 is a local data bus connected to the data output port of the peripheral device. 12o is a bus control device, 1
A path buffer 22 connects the system data bus to the local data bus and amplifies data signals. Reference numeral 123 denotes a change point detection section that detects voltage level fluctuations on the local data bus that affect the system data bus and outputs a change point detection signal TRG. 130c Decodes the data read signal RD on the system control bus and the address signal 5DR on the system address bus to generate the peripheral device selection signal SE.
This is a decoder that generates an L signal and a data read signal PRD. 124 receives the PRD signal generated by the decoder, and when a predetermined period of time for receiving the TRG signal of the change point detection section has elapsed, the pass buffer 124 outputs a connection signal GA between the system data bus and the local data bus.
This is a buffer control unit that provides 'rlC.

The operation of the bus control device configured as described above will be explained below with reference to FIGS. 1, 2, and 3.

First, FIG. 2 shows an example of a circuit of a bus control device according to an embodiment of the present invention, and FIG. 3 shows the timing of each part signal in FIG. 2. First, the decoder 130 decodes the MUDR signal on the system address bus 101 and provides the SKI signal to the peripheral device 110. Next, the Nitecoder 130 receives the RD double signal from the system control bus 100 and takes it from the peripheral device 1.
A data read signal PRD for 10 is output. After the peripheral device 110 receives the PRD signal and an access time has elapsed, the local data bus 121, 20
Change point detection units 123 and 220 detect fluctuations in the voltage level in the high impedance state of the local data buses 121 and 201 until DATA2 is outputted to DATA1. The change point detection unit 123.220 detects each hit D2n (n=Q,
1, 2. -..., 7) The voltage level fluctuations in the local data buses 121, 201 are brought close to the voltage levels in the high impedance state.
! The signal Dzn' (n=o, 1, 2, . Next, the above D2nl(n ”O+ 1 r 2 +...
..., by passing a) through the delay circuit 222, "2"
n'(n:o, 1, 2,...

7) is obtained. Next, the above Dzn' + D2n' (n
””0,1.

2, ・-・-・, 7) Signal-1) h et al. HX-O
Using the R circuit 223, a change point detection signal Pn (n=0.1.2..., 7) for each bit is obtained. Next, the above signal Pn(n""0, 1, 2 + "..."
+ 7 ) logical sum signal TRG to the 8-man OR circuit 22
4. As described above, the change point detection unit 123
．． The TRG signal obtained from 224 and the decoder 130
Using the obtained PRD signal, the buffer control unit 124゜2
30 generates a bus connection instruction signal GATE for the path buffers 122 and 2IQ. Buffer control unit 124
．． 230 is a two-man OR with retriggerable monomulti 231
Consisting of a circuit 232 and a local data bus 121, 2
When there is no change in the voltage level in the high impedance state of 01, that is, when the TRG signal is not output from the change point detection section 123, 224, the Q output of the IJ triple mono multi 231 is not generated, and therefore the decoder 130 At the timing when the PRD signal obtained by
01 is connected via a bus buffer 122°210. On the other hand, if a fluctuation occurs in the voltage level of the local data buses 121, 210 in the high impedance state,
That is, when the TRG signal is output from the change point detection unit 123, 224, the retriggerable monomulti 23 receives the TRG signal.
1 generates a q output during a specified time T, and inhibits the output of the (rAIK signal) of the 2-input OR circuit 232. After outputting the data, all bits D2n (n=o,
1, 2, --・-・−・.

7) After the signal is determined, the change point detection units 123 and 220
Since the RG signal is no longer output, the data set up time T required for the CPU to take in data from the system data bus 102゜200 at the rising edge of the RD signal is
Set the value to a value that is sufficient to ensure that.

As described above, according to this embodiment, uncertain fluctuations in the voltage level of the high impedance state on the local data bus are detected from the time when the peripheral device receives the data read signal until the time when the peripheral device outputs data to the local data bus. A buffer control unit is provided to completely inhibit the connection between the local data bus and the system data bus via the path buffer controlled by the CPU when the change point detection unit detects a voltage level fluctuation. By providing this, it is possible to prevent voltage level fluctuations occurring in the high impedance state of the local data bus from causing noise on the system data bus.

In addition, in the above embodiment, the change point detection unit 123°220
A delay circuit 222 and an EX
- Using the OR circuit 223, the logical sum of the detection results for each bit is used as the output of the change point detection section using the 8-man OR circuit 224. However, if the pulse width of the pulse output signal of the buffer circuit 221 is relatively wide, , the pulse obtained by differentiating the rising edge of the pulsed output signal is used as a change point detection signal for each bit, and the change point detection unit 123, 22 performs a wire FOR of the detection signal obtained for all bits.
It may be an output signal of 0.

Effects of the Invention As is clear from the above description, the present invention is effective in connecting the system data bus connected to the data output port of the central processing unit and the local data bus connected to the data output port of the peripheral device, and the data signal a path buffer that performs amplification; a change point detection unit that detects a change point in the voltage level on the local data bus; and a change point detection unit that detects a change point in the voltage level on the local data bus; By providing a buffer control unit that prohibits the central processing unit from controlling the connection between the system data bus and the local data bus performed by the controller, when the local data bus is in a zero impedance state, The reliability of the entire system is improved by preventing noise generation on the system data bus due to fluctuations in the voltage level of the system data bus, and by preventing noise generation on the system data bus from adversely affecting various nearby signal lines. can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a bus control device and its connection state in an embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific circuit example of the bus control device in FIG. 1, and FIG. FIG. 4 is a block diagram showing the connection state between a conventional CPU and peripheral devices, FIG. 5 is a timing diagram of signals in each section, and FIG. 6 is a waveform diagram of a specific operating state. 100...System control bus, 101
...System address bus, 102...
・System data bus, 11o... peripheral devices,
400... CPU, 121... Local data bus, 130... Decoder, 120...
... Bus control device, 122 ... Bus buffer, 123 ... Change point detection unit, 124 ...
...Buffer control section. Name of agent: Patent attorney Toshio Nakao and 1 other person f0
0---System control■-Lux 101=---System address bus 120---Bus control unit I /2/----Local tag 2g path f23---Ryokaretsu detection unit 2nd Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] Connecting the system data bus connected to the data input/output port of the central processing unit and the local data bus connected to the data output port of the peripheral device, and amplifying the data signal sent from the local data bus to the system data bus. a bus buffer that performs the operation, and a change point detection unit that detects a change point of the voltage level on the local data bus,
a buffer control unit that prohibits the central processing unit from controlling the connection between the system data bus and the local data bus performed by the bus buffer until a predetermined time has elapsed after the change point detection unit detected a voltage level change point; A bus control device comprising: