JPH0346048A - Data processing system - Google Patents

Abstract

PURPOSE:To improve the reliability of data by detecting the error of a signal owing to the change of an output value of the signal, informing a central processing unit of the error and restoring an initial value. CONSTITUTION:An error measurement device 4 detects the error in the output signals of respective bit lines in an address bus 2 so as to output an error detection signal by an edge detection circuit, and the error detection signal of an address signal outputted from the error measurement device 4 is inputted to the interruption terminal of MPU 1 through an interruption signal line 5 as an interruption request signal for a micro processor unit (MPU) 1. MPU 1 starts an interruption processing such as the re-output of the address signal, for example, and restores the output signal to the initial output value. Thus, the reliability of a data processing system can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing system that detects changes in the output content of a signal due to the incorporation of noise, etc., and prevents malfunctions.

[Conventional technology]

The structures of data processing systems are becoming more complex as data processing speeds increase, and malfunctions caused by changes in the output content of signals due to the incorporation of noise have a significant impact on data processing systems.

Figure 6 is, for example, "32-bit Microprocessor Introduction J (p. 15; CQ Publishing Co., Ltd., 198
7) is a block diagram showing an example of the configuration of a conventional data processing system, in which 1 is a microprocessor unit (hereinafter abbreviated as MPU),
MPUI outputs an address signal to address bus 2. The address decoder 9 decodes the address signal, and ANDs the decoded address signal and the address strobe signal (AS) output from the MPUI to the external device 3.
Output.

The read/write signal (READ/WRITE) and data strobe signal <DS) are output to the external device 3, and depending on the output level of the "READ/WRITE" signal, data is sent from the external device 3 to the data bus 8 or from the MPUI. A data signal is output to bus 8.

The read/write operations of the data processing system configured as above will be explained. In the read cycle, the MPUI
“READ/WRITE” signal to high level (“H”)
After outputting the address signal to address bus 2, “
AS" signal is set to "H". The address signal decoded by the address decoder 9 is sent to the external device 3, for example.
is specified, external device 3 is MPUI
outputs a data signal to the data bus 8 in response to setting the "DS" signal to "H'", and the MPUI takes in this data signal.

Also, in the write cycle, the MPUI
After setting the RITE' signal to low level (“L”) and outputting the address signal to address bus 2, the “AS” signal is set to “L”.
The MPU 1 outputs the data signal to the data bus 8, and if the address signal decoded by the address decoder 9 specifies, for example, the external device 3, the MPU 1 outputs the data signal to the data bus 8, and sets the “DS′” signal to “H”. ” and write data to external device 3.

[Problem to be solved by the invention]

Conventional data processing systems have the above configuration, so for example, even if the address signal changes due to the introduction of noise etc. after the MPUI outputs the address signal, the MPUI has a means to detect this change. without having
There is a problem in that data reliability is low because data is read or written to an incorrect address, resulting in malfunction.

The present invention has been made to solve such problems, and the present invention detects signal errors caused by changes in the output value of the signal, notifies the central processing unit, and restores the original value. Our goal is to provide a highly reliable data processing system.

[Means to solve the problem]

The data processing system of the present invention includes a means for detecting the occurrence of a change in an output signal whose output value has changed due to the incorporation of noise or the like during its effective period, and notifying a signal output light circuit; The present invention is characterized in that it includes means for restoring the output signal to its original value by, for example, interrupt processing, re-output, or the like.

[Effect]

The data processing system of the present invention detects the occurrence of a change when the output value of the signal changes from its initial value due to the introduction of noise etc. during the valid period of the output signal, and transmits the signal to the circuit that is the output light of the signal. Notify the occurrence of a change and restore the output value of the signal to its original value.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on drawings showing embodiments thereof.

FIG. 1 is a block diagram showing the configuration of a data processing system according to the present invention. In this embodiment, errors in address signals are detected. In the figure, 1 is an MPU, and the MPUI outputs an address signal to an address bus 2. The address signal output to the address bus 2 is output to the external device 3 via the error countermeasure device 4 and the system bus 7. An address strobe signal (AS) and a data strobe signal (DS) are output to the external device 3 via the system bus 7. The data signal is output from the external device 3 to the data bus 8 via the system bus 7 or from the MPU 1 to the data bus 8 depending on the read or write cycle. The error countermeasure device 4 detects an error in the output signal of each focus line of the address bus 2 using an edge detection circuit or the like and outputs an error detection signal. The error detection signal is input to the interrupt terminal of the MPUI via the interrupt signal line 5 as an interrupt request signal to the MPUI.
The PUI starts interrupt processing, such as re-outputting an address signal, for example.

2 and 4 are circuit diagrams showing the configuration of an edge circuit which is an example of the bottom of the error countermeasure device 4, and FIG.
FIG. 4 is a circuit diagram showing the configuration of a fall detection circuit that detects an error in the "H'" signal. The rising detection circuit (FIG. 2) includes a three-stage N07 circuit provided as a buffer that also serves as an inversion of the logic level of the input (A) to the error countermeasure device 4, and a falling detection circuit. It consists of an AND circuit which takes the input signal A as one input and takes the signal B inverted by the three-stage N07 circuit as the other input.

In addition, the fall detection circuit (Figure 4) includes a four-stage N07 circuit provided as a buffer that also serves to invert the logic level of the input signal to the device, and a signal in which the input signal is inverted by the N07 circuit. and input the input signal to the N of the four stages.
AND with the signal E inverted by the 07 circuit as the other input
Consists of circuits.

The outputs of the rising detection circuit and falling detection circuit connected to all address bits are ORed, and the output becomes “H”.
In this case, it is output as an interrupt request signal to MPUI.

Next, the edge detection operations of the rising edge detection circuit and the falling edge detection circuit will be explained based on the timing charts of FIGS. 3 and 5. “L” during the valid period of the address signal.
The rising edge detection circuit monitors the "H" signal, and the falling edge detection circuit monitors the "H" signal.

When the rising detection circuit that monitors the "L" signal is normal, the human power B is "H" and the output C is "L";
When noise is mixed into the address signal that should be the same, the input signal A rises as shown in FIG. 3, and one input of the AND circuit changes from ``L'' to ``H''. At that time, the other input B continues to be at the initial "H" level without following the change in A while the signal passes through the three-stage N07 circuit, so the output C of the AND circuit is an "H" signal. Changes to . Thereafter, the B input changes from "H" to "L" with a delay, and the output C returns to 'L'.

In addition, during normal operation of the falling detection circuit that monitors the 'H' signal, the input E is 'H' and the output F is 'L'.
If noise mixes into the address signal that should be ``H'', the input signal will fall as shown in Figure 5, and the input signal will be inverted.
One input of the ND circuit changes from "L" to "H". At this time, the other input E does not follow the change in D while the signal passes through the N07 circuit and continues to be at the initial "H" level, so the output F of the AND circuit changes to an "H" signal.

After that, the E input changes from H" to L" with a delay, and the output F
returns to "L".

Although this embodiment has been described as a countermeasure against errors in address signals, the present invention is not limited to address signals, and can be applied to countermeasures against errors in any other signals, and similar effects can be obtained.

[Effects of the Invention] The data processing system of the present invention includes a means for detecting a signal error between circuits, and when an error is detected, requests the signal output source to perform re-output 1 interrupt processing, etc., and outputs the output signal. The configuration is such that the output value is restored to the original value, and has the excellent effect of improving the reliability of the data processing system.

[Brief explanation of drawings]

The cabinet 11118 is a block diagram showing the bottom of the data processing system according to the present invention, FIGS. 2 and 4 are circuit diagrams showing an embodiment of the main part thereof, and FIGS. 3 and 5 are diagrams of the output signals thereof. Timing chart FIG. 6 is a block diagram showing the configuration of a conventional data processing system. 1...MPU 2...Address bus 3...External device 4...Error countermeasure device 5...Interrupt signal line 7...System bus 8...Data bus Note that the same lines in the diagram Codes indicate the same or corresponding parts.

Claims (1)

[Claims] (1) In a data processing system consisting of a group of circuits that transmit and receive signals, a means for detecting the occurrence of a change in an output signal to a signal with a different output value and notifying the circuit from which the signal is output, and a means for notifying the occurrence of the change. and means for restoring the output value to the original value according to the request.