JPH0385661A - Dynamic access time control data processor - Google Patents

Abstract

PURPOSE:To perform an access without fail even concerning a peripheral equipment, for which address set-up operation is delayed, by extending an address period and a read period when an LPS signal showing the equipment with the delayed operation becomes a specified logical level. CONSTITUTION:When an address from a CPU 1 designates an external equipment, which address can be set up at normal speed, excepting for a low-speed peripheral equipment 4, the LSP signal from a decoder 2 is set 'L' and operation such as address set-up and data read, etc., is executed at normal speed. When an address designating the low-speed peripheral equipment 4 is outputted from the CPU 1, according to the address code, the LSP signal is made 'H' by the decoder 2. By this signal at the 'H' level, the address signal from the CPU 1 is extended for prescribed time and the long address signal is obtained in the low-speed peripheral equipment 4. Thus, the address set-up of the low- speed peripheral equipment 4 correctly is executed as well.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data processor, and more particularly to a data processor capable of reading data from slow-operating peripheral devices.

In conventional microprocessors, when reading or writing data from a peripheral device, the peripheral device is accessed by an address output from the microprocessor during a predetermined address period, the address is set up, and the data is read out to the microprocessor. Perform this work.

Problems to be Solved by the Invention In this type of microprocessor system, the access time of peripheral devices such as memory peripherals differs depending on the type, on-chip, etc. However, it is difficult for a microprocessor to dynamically adjust its access time to peripheral devices that have different access times.

In conventional microprocessors, M
Since a wait cycle is entered only in the second half of the access time due to inputs such as RDY and WAIT, peripheral devices whose specifications are slow in the first half of the access time, such as address set-up, cannot be accessed.

The present invention has been made to solve the above-mentioned problems, and is capable of reliably operating peripheral devices having a predetermined access speed, and easily and reliably operating peripheral devices having a slow access speed. The purpose is to provide a microprocessor that can access

Means for Solving the Problems The data processor of the present invention outputs an address specifying a device to be accessed from an address terminal during an address period, and reads data from the specified device (
In the microprocessor that receives the LSP signal at the read terminal during the reading period, the terminal that receives the LSP signal indicating that the device is operating slowly is terminated;1. S l) Shinkyuriki side? The feature is that when the processing level reaches a certain level, the address period and the read period are extended.

Embodiment In FIG. 1, 1 is a CPU using a microprocessor.
, 2 is the decoder, 3 is the RAM, ! =ROM.

4 is a low-speed peripheral device 2g.

Similar to a normal microprocessor, the CPU has various terminals AO to AI5 shown in FIG. 3. Address bus outputs BAO to BA7: Bank address bus output BE' bus enable input CLK. Data bus input/output DA, data/address output IRQ: Interrupt input l5EO, l5EI/IRQ selection input ML, memory lock output 11M+ Non-maskable interrupt input PA
・Program address output R11l read
Bar output RES Reset interrupt input RWB
Read/write outputs Sl, S2 - Synchronous clock output JVTA - Vector address table output WAIT: Equipped with processor stop input WB and write bar output. Then, the address specifying the device to be accessed is output from the 71-less terminal during the address period, and the data from the specified device is read.
The data received and read into the lead terminal during the period is processed according to a predetermined program.

The CPUI further includes a terminal LSP for receiving an LSP signal for activating low-speed peripheral devices.

In this invention, the CPUI operates in the same manner as a conventional microprocessor when the LSP terminal is "I7". On the other hand, when the above LSP terminal is set to H level, 1/
Slows down CPUI operation by two bus cycles. In this embodiment, the “L” portion of the synchronous clock S1 and the “H” portion
``The address period is extended by 1/4 cycle of the synchronous clock S1 in both parts, and as a result, the address period is also extended by 1/2 cycle of the synchronous clock S1 compared to the length AL when the LSP signal is low. As a result, the read period RD is also extended, and the period ts that can be used for address setup is also longer than the cent-up period ts during which the LSP signal is "L". This makes it possible to support devices that have a slow address setup part in the first half of the access time.

Also, unlike the normal WAIT terminal, the LSP terminal is
The cycle does not continue to be delayed for a period of L″″.
When it goes to "H", there is a delay of 172 bus cycles.As a result, the LSP terminal becomes
It is not necessary to release the CPU and continue executing the CPUI.

In the embodiment described above, the signal LSP is obtained by decoding the address output from the CPU 1 with the decoder 2 if the address is indicative of the low-speed peripheral device 4. According to the above-mentioned device, if the address from the CPUI specifies an external device (not shown) capable of address setup at normal speed (high speed) other than the low-speed peripheral device 4, the LSP from the encoder 2 is The signal is °'
L°'', operations such as address setup and data reading can be obtained at the normal speed shown in the left half of FIG.

Now, when the CPU outputs an address specifying the low-speed peripheral device 4, the encoder 2 sets the LSP signal to "H" in order to use that address code.

This "'l-1" level signal extends the AH time of the address signal from the CPU, providing a long address period for the low-speed peripheral device 4, and allowing the address setup of the low-speed peripheral device 4 to be performed correctly. .

Note that the signals r and sp are not limited to the method of decoding address signals as in this embodiment, but may be produced by other methods.

Effects of the Invention As described above, the present invention makes it possible to delay the first half of the access time such as address set-up, and even peripheral devices whose address set-up operation is slow can be reliably accessed.

Further, according to this invention, even if the weight is not released, 1
Another advantage is that the LSP state is automatically released after /2 bus cycles.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a time chart showing the operation of the main parts of FIG. 1, FIG. 3 is a diagram showing the terminals of the embodiment of FIG. 1, and FIG. 5 and 5 are time charts showing the operation of the conventional device.

Claims (1)

[Claims] (1) The microprocessor outputs an address specifying the device to be accessed from the address terminal during the address period and receives data from the specified device at the read terminal during the read period, and the device must operate slowly. It has a terminal that receives an LSP signal indicating LS
A dynamic access time control data processor characterized in that an address period and a read period are extended when a P signal reaches a specific logic level.