JPS6177770A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To facilitate the checking for poor operation of a circuit and a system, by outputting a signal outside to control the low impedance state and the high impedance at the 3-state output. CONSTITUTION:When the output control signal -E is '0' or the data signal D is '0', outputs of gates 15 and 16 move to '1' to turn OFF a MOSFET17 while a MOSFET18 is turned ON and an L level is outputted at a terminal 12. When the signal -E is '0' or the signal D '1'. The terminal 12 moves to H level and moreover, when the signal -E is '1', the terminal 12 turns to a high impedance state. The line for feeding the signal -E is connected to an output terminal 24 for outside through inverters 231 and 232 acting as control signal outputting circuit 22 to fetch the signal -E from the terminal 24.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit device having a three-state data output terminal.

[Technical background of the invention and its problems]

Conventionally, a data output circuit of a three-state buffer in this type of semiconductor integrated circuit device has been implanted, for example, as shown in FIG. That is, the data output circuit 11 receives an output control signal E and a data signal from inside the device, and outputs a high (-H") signal based on these signals E and D.
) level, low (@L#) level, high impedance state, and a signal in three states is outputted to the external data line (BUS) 13 via the output terminal 12. The above data output circuit 1
1 is a NAND 15 in which a data signal is supplied to one input terminal, and an output control signal E is supplied to the other input terminal via an inverter 14; a P-channel MOS FET J7 connected between the power supply vDD and the output terminal 12 and whose conduction is controlled by the output of the Nand Dart 15, and An N-channel MOS connected between the output terminal 12 and the ground point V8s and whose conduction is controlled by the output of the NOR gate 16.
It is made up of one FET 1B.

The operation in the above-mentioned formation will be explained.

First, when the output control signal E is at the "0" level and the data signal is at the @0 level, the NAND r-to 15 and the NAND f-
Since the outputs of ports 16 and 16 are respectively at the "l# level,"
, (O8FET 17 if off state, hqosFE
T18 is turned on. Therefore, the output terminal 12 outputs the Vss (“L”) level.

Next, when the data signal goes to the 11# level while the output control signal 100 is at the "O" level, the outputs of the Nant gate 15 and the NOR gate 16 each go to the "0# level."

As a result, MOS FET12 is turned on, and the MOS
FET 1 B is turned off, and the output quadrature 12 outputs the vDD (“L”) level. On the other hand, when the output control signal E becomes "1" level, the output of the NAND gate 16 becomes "1# level" and the output of the NOR gate 17 becomes "0" level, regardless of the level of the data signal. Therefore, the MOS FET 17 , 18 are both off, and the output terminal 12 is set to a high impedance state.

By the way, the above-mentioned three-state buffer is widely used as a data and path driving circuit in, for example, EVA micro, computer, and systems. In this case, one data path is connected to the CPU, memory, three states for LSI such as 10, and a buffer to exchange data. For this reason, only the potential of the data path is detected. However, there is a drawback that it is not known which LSI the output circuit of which potential is provided is the output of. Furthermore, if data is being output from two or more output circuits due to malfunction, etc., it cannot be confirmed.

Figure 9 shows a conventional microcomputer.

FIG. 2 is a diagram for explaining data transfer in the system. The external data line (BUS) 13 includes a central processing unit ff1 (CPU) J9. Multiple memory devices 2 ol
Input/output terminals such as r 202 + 203 and a seed kLD peripheral device (r7'o) 21 are connected thereto. In addition, from the CPU 19, other devices 2
Data control signal wind is output to 0H+21172+203 and 2no. Now, the above data control signal wind is “
If the memory device 201 + 2 is at O” level, the memory device 201 + 2
02. The output circuits provided in 203 and peripheral device 2 are in a high impedance state, and BUS 13 has a C
Only output from PU 19 is allowed. On the other hand, when the data control signal wind reaches the "1# level", the device 20H+20z
* Any one of the output circuits in 203 and 21 is set to a low impedance state, and the CPU 19
receives data from the device @ However, in the above configuration, the data control signal wind is “
0'' level, it is not known whether data is being output from the CPU 19 or whether it is in a high impedance state, so other devices 2θI N'202 N2 may be affected by noise etc.
If O3;h or 21 accidentally outputs data to BUS 13, even if the CPU 19 does not output data, other devices may receive the data. Furthermore, even when the data control signal wind is at the 11" level, the memory device 201 +202 +20
Malfunctions may also occur, such as when neither peripheral device 3 nor peripheral device 2 outputs data, or data is output from a plurality of devices. Thus, the memory device 2θl, 2
Since the 0□, 2o3 and the peripheral device 21 do not have a terminal for outputting the output state to the outside, it is difficult to check for defects inside the device or when configuring the system.

[Purpose of the invention]

This invention was made in view of the above circumstances,
The purpose is to provide an entire semiconductor integrated circuit device that can easily detect circuit malfunctions and check the system by outputting the data output state to the outside.

[Summary of the invention]

That is, in the present invention, in order to achieve the above object, a semiconductor integrated circuit device is provided with a terminal for externally outputting a control signal for controlling the low impedance state and high impedance state of the three-state output. be.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, the same components as those in FIG. 8 are given the same reference numerals, and detailed explanation thereof will be omitted. That is,
A line to which the output control signal E is supplied is connected to an output terminal (control signal output terminal) 24 to the outside via inverters 231 to 23z'x each functioning as a control signal output circuit 22.

According to such a configuration, since the output control signal r can be taken out from the output terminal 24, the data output state of the semiconductor integrated circuit device can be known from the outside, and it is easy to check malfunctions of the circuit and the system. You can go to

For example, in the case of microcontrollers, computers, and systems as shown in Figure 8 above, data may be output from two or more devices even though one device is accessed, or data may be output from any device even if accessed. When no output occurs, the malfunctioning device can be easily discovered. Therefore, depacking on the system becomes possible.

Note that, as shown in FIG. 2, a plurality of data output circuits 111 to 114 are provided in the same LSI, and each of these data output circuits If1 to 114 is provided with different data DBo.
~DB3 and the common output control signal E are supplied to the control frlI signal output circuit 22 and the output terminal 24.
It is sufficient to provide one each.

As described above, by providing the output terminal 24 that outputs the output control signal E'Q, if the CPU requests a specific device to output data but no data is output, this CPU IC allocation It is also possible to invalidate the imported data by performing an import. That is, as shown in FIG. 3, the data control signal NI output from the CPU 25
R and the output control signal i of the device 26 are respectively supplied to an AND gate 27, and the output of this AND gate 27 is connected to CP.
The interrupt terminal INT IC of U25 is supplied to generate an interrupt. As a result, the CPU 25 learns that no data has been output, and performs processing accordingly.

Figure 4 shows that when the CPU requests data output from other peripheral devices but no data is output from any device, the output control signal detection circuit detects this and issues a CPU busy interrupt. This is what I decided to do.
CPo 25 and peripherals 261 +262 +26
3 m...The input and output terminals are connected by the melt bus 28, respectively. Each unit from the above CPU 25 ft
26. +ze, +263... are supplied with data control signal wind, and each device R2e1262... 263,・
The output control signal E output from ... is ANDff -)
29 respectively.

The output of this AND gate 3θ
is supplied to one input terminal of the CPU, and the other input terminal is supplied to the CPU
A data control signal output from 25 is supplied. The output of the AND gate 30 is then supplied to the interrupt terminal INT of the CPU 25. In addition, and dirt 2
9.30 constitutes the output control signal detection circuit 31t. According to such a configuration, the CPU 25 knows that no data has been output by inputting the interrupt terminal INT Ic "1", and can perform processing accordingly. CPTJ 25 is another peripheral device 261 .

262+263, . . . and when data is output from two or more devices, an interrupt is made to the CPU 25. CPU 25 and peripheral devices 261.

262. 263+...The input and output terminals are connected by the melt bus 28, respectively. Above CPU
The data control signal wind output from 25 is transmitted to each device 261.
+262 +26g +... and supplied to the controller 32. The controller 32Vc is
An output control signal E is supplied from each of the devices 2e 1 1 J 62 1263+=・, and when data is output from two or more devices, an interrupt signal is supplied to the interrupt terminal INT of the CPU 25. There is.

On the other hand, FIG. 6 shows that if data is output from any device while the CPU zs is not issuing a data output request, an interrupt is sent to the CPU 25 (or other device) to retrieve the data. This invalidates the data. This circuit has a 0 state similar to the circuit shown in FIG.
The only difference is that it is supplied to 0.

In FIG. 7, when data is output from a plurality of peripheral devices, the device with the highest priority is selected from among them, its output is acquired, and the output of the other devices is stopped.

That is, the data control signal output from the CPU 25 is transmitted to the peripheral device 261 and the AND/DART 341+34.
2 +343, . . . are supplied to the negative input terminals. above) 341 1342 +343 +...
The output control signal E output from the peripheral devices up to the previous stage is supplied to the other input terminals of . It looks like this.

As a result, the first priority position is peripheral equipment fR261+262
+263, ;j64, . . . are set in this order.

By providing a terminal for outputting internal control signals in this manner, various functions as shown in FIGS. 3 to 7 can be added.

〔Effect of the invention〕

As described above, according to the present invention, since means for outputting the data output state to the outside is provided, it is possible to obtain a semiconductor integrated circuit device in which circuit malfunctions and system checks can be easily performed.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining a semiconductor integrated circuit device according to one embodiment of the present invention, FIGS. 2 to 7 are diagrams for explaining other embodiments of the present invention, and FIG. 9 and 9 are diagrams for explaining a conventional semiconductor integrated circuit device, respectively. DESCRIPTION OF SYMBOLS 11... Data output circuit, 12... Data output terminal, 24... Control signal output terminal, D... Data signal,
E...Output control signal. Applicant's Representative Patent Attorney Takehiko Suzue Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] A semiconductor integrated circuit device having a three-state data output terminal to the outside, characterized in that it is provided with means for outputting an internal control signal for controlling the low impedance state and high impedance state of its output to the outside. circuit device.