KR20000003736A - Semiconductor memory device with skew reducing circuit - Google Patents

Abstract

PURPOSE: It is to minimize the skew of drivers in a semiconductor memory device. CONSTITUTION: The skew reducing circuit comprises a skew sensing section(131) and a capacitance controlling section(141). The skew sensing section and the capacitance controlling section are connected to a driver(111, 112), and a interior circuit(121) are connected to output terminal of the drivers. The drivers are operated by receiving a signal from the semiconductor memory device. Size of the drivers are determined according to a gate capacitance and a bus line capacitance of a transistor.

Description

Skew Reduction Circuit of Semiconductor Memory Device

TECHNICAL FIELD The present invention relates to semiconductor memory devices, and more particularly to skew reduction circuits.

BACKGROUND ART With the recent trend of increasing the speed of systems using semiconductor memory devices, semiconductor memory devices have also become increasingly faster and wider. In order to speed up and widen the semiconductor memory device, the semiconductor memory device may operate normally only when skew of main signals inside the semiconductor memory device is several tens of pico seconds or less.

Conventionally, the output stage loading of an inverter driver for driving an internal circuit is mainly a gate capacitance and a bus line capacitance of a transistor connected to the output stage. However, when the output terminals are connected to different circuits so that the gate capacitance and the bus line capacitance of the transistor are different, skew occurs when the signals are enabled. The skew often has a great influence on the characteristics of the high-speed and wide-area semiconductor device, so it must be designed as small as possible.

An object of the present invention is to provide a semiconductor memory device having a skew reduction circuit for minimizing skew of drivers.

1 illustrates a skew reduction circuit and a driver of a semiconductor memory device according to a preferred embodiment of the present invention.

FIG. 2 is a timing diagram of the signals shown in FIG.

The present invention to achieve the above technical problem,

A semiconductor memory device having at least two adjacent drivers for driving an internal circuit, the semiconductor memory device comprising: a skew sensing unit sensing skew of outputs of the drivers and output terminals of the drivers and responsive to an output of the skew sensing unit; And a capacitance adjuster for adjusting capacitance values of outputs of the semiconductor memory device.

The skew of the drivers is reduced by the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a skew reduction circuit and a driver of a semiconductor memory device according to an exemplary embodiment of the present invention. Referring to FIG. 1, a skew reduction circuit of a semiconductor memory device according to an exemplary embodiment of the present invention includes a skew detector 131 and a capacitance adjuster 141. Drivers 111 and 112 are connected to the skew detecting unit 131 and the capacity adjusting unit 141, and internal circuits 121 are driven by inputting the outputs of the drivers 111 and 112 to the output terminals of the drivers 111 and 112. Is connected.

The drivers 111 and 112 receive and drive signals from inside or outside the semiconductor memory device. Drivers 111 and 112 are typically sized according to the size of the loads connected to the output stages. If there is an optimum point to reduce the skew of the output terminals of the drivers 111 and 112, the size of the drivers 111 and 112 to match the gate capacity and the bus line capacity of the transistor (not shown) connected to the output terminal, respectively. Is determined.

The skew detector 131 detects skew of output terminals of the drivers 111 and 112. The load of the output terminals of the drivers 111 and 112 is mainly based on the gate capacitance and the bus line capacitance of the transistors of the internal circuits 121 connected to the output terminals of the drivers 111 and 112. However, when different circuits are connected to the output terminals of the drivers 111 and 112 and the gate capacitance and the bus line capacitance are different, skew occurs between the signals CLK_A and CLK_B. The skew detector 131 detects the skew. When the load of the signal CLK_A is large, the output signal CAPA_EN0 of the skew detector 131 is enabled as '1', and the output signal CABB_EN0 becomes '0'. When the load of the signal CLK_B is large, the output signal CAPB_EN0 of the skew detector 131 is enabled as '1', and the output signal CAPA_EN0 is set to '0'.

The skew detector 131 includes a flip-flop 151, inverters 161 to 164, transmission gates 171 and 172, and latches 181 and 182. The flip-flop 151 inputs the signals CLK_A and CLK_B. Inverters 161 and 162 are connected to the output terminal of flip-flop 151, respectively, to invert the output of flip-flop 151, respectively. The transfer gates 171, 172 are gated by the outputs of the latches 181, 182, respectively. That is, the transfer gate 171 is turned on when the output of the latch 181 is '1', and the transfer gate 171 is turned off when the output of the latch 181 is '0'. )do. In addition, when the output of the latch 182 is '1', the transfer gate 172 is turned on. When the output of the latch 182 is '0', the transfer gate 172 is turned off. Inverters 163 and 164 invert the outputs of latches 181 and 182, respectively, to generate output signals CCAP_EN0 and CAPB_EN0, respectively.

The capacitance adjuster 141 adjusts capacitance values of the outputs of the drivers 111 and 112 in response to the output signals CCAP_EN0 and CABP_EN0 of the skew detector 131. The capacitance adjusting unit 141 includes an NMOS transistor 191 connected to an output terminal of the driver 111, a capacitor 195, and an NMOS transistor 192 connected to an output terminal of the driver 112 and a capacitor 196. The NMOS transistors 191 and 192 are gated by the output signals CAPA_EN0 and CABP_EN0 of the skew detector 131, respectively. When the output signal CAPA_EN0 of the skew detector 131 is enabled as '1', the transistor 191 is turned on to increase the load of the signal CLK_A so that the loads of the signals CLK_A and CLK_B are similarly adjusted. In the same way, when the output signal CAPB_EN0 is enabled as '1', the transistor 192 is turned on to increase the load of the signal CLK_B, thereby matching the loads of the signals CLK_A and CLK_B.

FIG. 2 is a timing diagram of the signals shown in FIG. 1. As shown in FIG. 2, when the load of the signal CLK_A is greater than the signal CLK_B, the output signal CAPA_EN0 of the skew detector 131 is enabled as '1', and the output signal CABP_EN0 is enabled. Disabled to '0'.

The best embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, when the loads of the output terminals of the drivers 111 and 112 are different because the number of circuits 121 connected to the output terminals of the drivers 111 and 112 or the bus line capacity are different, the skew detector ( 131 operates to selectively turn on the transistors 191 and 192 of the capacitance adjusting unit 141 to similarly load the output terminals of the drivers 111 and 112, thereby reducing the skew between the signals CLK_A and CLK_B to a minimum.

Claims (1)

A semiconductor memory device having at least two adjacent drivers for driving an internal circuit, the semiconductor memory device comprising: A skew detector for detecting skew of outputs of the drivers; And And a capacitance adjusting unit connected to output terminals of the drivers and configured to adjust capacitance values of the outputs of the drivers in response to an output of the skew detector.