JPS57117058A - Composite computer - Google Patents

Composite computer

Info

Publication number
JPS57117058A
JPS57117058A JP267481A JP267481A JPS57117058A JP S57117058 A JPS57117058 A JP S57117058A JP 267481 A JP267481 A JP 267481A JP 267481 A JP267481 A JP 267481A JP S57117058 A JPS57117058 A JP S57117058A
Authority
JP
Japan
Prior art keywords
data
storing
memory
signal
system bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP267481A
Other languages
Japanese (ja)
Inventor
Kenji Shoroji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP267481A priority Critical patent/JPS57117058A/en
Publication of JPS57117058A publication Critical patent/JPS57117058A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To unify input/output circuits and to execute the processing irrespective of a processing time, by coupling each microprocessor unit through a common bus, and providing an FI/FO memory circuit. CONSTITUTION:The SEND side is provided with a priority process-part 3-1 for controlling a transmission request signal REQ, an acknowledgement signal ACK and a system bus state signal BBSY, an FI/FO memory part 3-2 for storing a series of data, a block ready part 3-3 for showing a block data storing state, and a clock controlling part 3-4 for sending out data one by one. On the other hand, the REC side is provided with a part 3-5 for discriminating whether the system bus is in use or not, a signal checking part 3-6, an FI/FO memory part 3-7 for storing receiving data, and an interruption generating part 3-8 for making an MPU start to read.
JP267481A 1981-01-13 1981-01-13 Composite computer Pending JPS57117058A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP267481A JPS57117058A (en) 1981-01-13 1981-01-13 Composite computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP267481A JPS57117058A (en) 1981-01-13 1981-01-13 Composite computer

Publications (1)

Publication Number Publication Date
JPS57117058A true JPS57117058A (en) 1982-07-21

Family

ID=11535852

Family Applications (1)

Application Number Title Priority Date Filing Date
JP267481A Pending JPS57117058A (en) 1981-01-13 1981-01-13 Composite computer

Country Status (1)

Country Link
JP (1) JPS57117058A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62224850A (en) * 1986-03-26 1987-10-02 Hitachi Ltd Interface device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62224850A (en) * 1986-03-26 1987-10-02 Hitachi Ltd Interface device

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