JPS62224850A - Interface device - Google Patents

Abstract

PURPOSE:To speed up the data transmission by providing a transmission buffer memory and a reception buffer memory separately. CONSTITUTION:The titled device 31 is comprised of the transmission buffer memory 4000, the reception buffer memory 4001, a control part 401, an address register 4020 for transmission buffer memory, and an address register 4021 for reception buffer memory. The storage capacity of the device 31, together with those of the memories 4000 and 4001, is set at a size to cover the maximum amount of one-time data transfer between respective data processing equipments. By separating the memories 4000 and 4001 from each other, the transfer of transmission/reception data to different data processing equipment and that to the equipment itself, can be executed simultaneously. Hence the data transfer can be speeded up.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an interface device for connecting data processing devices, and particularly to an interface device suitable for high-speed data transfer.

[Background of the invention]

FIG. 2 is a block diagram of a data processing system, in which a master data processing unit (DPEO) 10 is connected via a bus 2.
Slave data processing devices 11 to 1n are connected. Each slave data processing device 11 to 1n is composed of an interface device (IFB) 41 to 4n and a data processing unit (DPU) 31 to 3n, respectively. Even if there is one, the interface devices 41 to 4n make it compatible with a multi-bus system.

FIG. 3 shows the conventional configuration of the above-mentioned interface device. The data processing unit 31 to which the conventional interface device 41 is connected is a microprocessor type data processing unit, and the central control unit (CPU) 3
00, a main memory unit (MM) 301, a direct memory access control unit (DMAC) 302, and an external storage unit and console unit (not shown), which are connected to a data bus 303 and an address bus 304.
is connected with. The conventional interface device 41 includes a buffer memory (BM) 400 and a control unit (CTL).
401 and the buffer memory address pointer (BAP
) 402, the data bus 21 and the control bus 22
The data processing unit 31 is connected to the data bus 303 and the address bus 30 via the bus 2 (Fig. i2).
4, the control unit 401 and the central processing unit 300
An interrupt line 500 is provided between the two. The storage capacity of the buffer memo IJ 400 is normally only large enough to buffer differences in data transfer speeds among the data processing devices 10.12 to 1n.

Data sent from the bus 2 via the data bus 21 is sent to the buffer memory 400 under the control of the control unit 401.
is stored in Buffer memory address pointer 402
Since the value initially indicates the starting address of the buffer memory 400, the data sent first is written to the starting address of the buffer memory IJ 400. From then on,
The contents of the buffer memory address pointer 402 are updated under the control of the control unit 401, and data sent via the data bus 21 is sequentially transferred to the buffer memory 400.
will be written into. When there is no more data input via the data bus 21, the control unit 401 uses the interrupt line 500 to
The buffer memo IJ is sent to the central control unit 300 via
A read instruction signal for data within 400 is sent. The central control unit 300 drives the direct memory access control unit 302 under the control of a program stored in the main memory unit 301, and transfers the data in the buffer memory 400 to the main memory unit 301 and the data bus 30.
3 and read via address bus 304. In this way, data transfer from the master data processing device IO is executed.

Conversely, data transfer from the data processing unit 31 to the master data processing device 10 is performed as follows.

From the main memory unit 301 of the data processing unit 31,
Under the control of direct memory access control unit 302, data is sent to buffer memory IJ 400 via address bus 304 and data bus 303. This data is sequentially written from the top address of the buffer memory 400 as described above. When there is no more data sent from the main memory unit 301 via the data bus 303, the control unit 401 instructs the master data processing device 1o to read the data in the buffer memory 400 via the control bus 22, and processes the master data. In response, device 1o reads the data in buffer memory 400.

When this is completed, the control section 401 notifies the central control unit 300 of the end of transmission through the interrupt line 500)k.

As mentioned above, since the conventional interface device uses the buffer memory IJ 400 for both transmission and reception, the data input via the data bus 21 and the data input via the data bus 303 are The configuration is such that it is not possible to import data at the same time, and the only option is to perform half-duplex transfer. Also, care must be taken to ensure that data exceeding the capacity of the buffer memo U 400 is not sent at one time. For this reason, conventional interface devices have a problem in that they are not suitable for high-speed data transfer.

In addition, related to this crosspiece device, Masaido Publishing “
"Design of Combiator System" by Hiroshi Hatata, pp. 28-30 describes the trap buffer memory system.

[Purpose of the invention]

An object of the present invention is to provide an interface device that can handle high-speed data transfer without complicating the hardware configuration.

[Summary of the invention]

In the present invention, the transmission buffer memory and the reception buffer memory are separated, and transmission or reception data transfer to another data processing device and reception or transmission data transfer to the own data processing device can be executed simultaneously. Measure to speed up transfer. In addition, an address register for transmitting buffer memory and an address register for receiving buffer memory that can be accessed from the own data processing device are provided, so that any address in the transmitting or receiving buffer memory can be accessed from the own data processing device, and the data processing We aim to improve the flexibility of connections between devices. In addition, the storage capacity of the transmitting and receiving buffer memory is set to a capacity that can store the maximum amount of data transferred in one data transfer between each data processing device, and the data transfer speed of each data processing device is different. Also, interface devices with the same node configuration can be used.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 is a block diagram of a slave data processing device equipped with an interface device according to an embodiment of the present invention. Since the data processing unit 31 shown in FIG. 1 has the same structure as that explained in FIG. 3, the same reference numerals will be given and the explanation of the structure will be omitted.

w, The interface device 31 shown in Figure 1 includes a transmission buffer memory (8BM) 4000, a reception buffer memory (RBM) 4001, a control section 401, an address register for transmission buffer memory (8AR) 4020 and 8, and an affection buffer memory. Use address register (RAR,) 4
021, and the storage capacity of both the sending buffer Ameshichi J 4000 and the receiving buffer memo IJ 4001 is equal to the maximum amount of data transferred at one time in data transfer between each data processing device.

When data is sent from the master data processing device,
If there is data to be sent to the master data processing device,
In the interface device 31 of this embodiment, as follows,
The data sent from the master data processing device is stored in the reception buffer memory 4001, and at the same time, the data sent from the main storage unit 301 (also stored in the transmission buffer memory 1J4000).

Under the control of the control unit 4010, data transmitted from the master data processing device via the data bus 21 under the control of the control bus 22 is written into the reception buffer memory 4001. Since the value of the first receive buffer memory address register 4021 indicates the start address of the receive buffer memory 4001, the first data sent is written to the start address of the receive 18 buffer memory 1J4001. Thereafter, the contents of the address register 4021 are updated under the control of the fiflJ(41 unit 401), and the data transmitted via the data bus 21 is sequentially stored in the reception buffer memory 4001 (. When there is no more data transmitted via the data processing unit 4001, the control unit 401 issues an instruction to the central control unit 300 via the interrupt line 500 to clean up the data in the reception buffer memo 1J4001. The transmission buffer memory 40 is controlled by the direct memory access control unit 302 from the memory 1i 1301.
00K data is sent to address bus 304 and data bus 30
Sent via 31. Initially, this data is i
& First sent data (1 send 1 Tombuffer memory 4
000 is the first address. From now on, control m54
The contents of the address register 4020 are updated by the 1 [# of 01, and the data transmitted via the data bus 303 is stored in the J@ next transmission buffer memory 40.
It is written to 00.

Central control unit 300 instructed to read data in reception buffer memory 4001 via interrupt @SOO
is the IFs Yu buffer memo from the main memory unit 301!
After data writing to the J4000 is completed, the direct memory access control unit 302 is driven under the control of the program stored in the main memory unit 301, and the data is accessed according to the address of the receive buffer memory address register 4021. Then, the data in the reception buffer memory 4001 is read into the main storage unit 301.

After writing data to the transmission buffer memory 1J4000, the control unit 401 instructs the master data processing device to read the data in the transmission buffer memory 4000 through the control path 22, and the master data processing device responds to this by instructing the master data processing device to read the data in the transmission buffer memory 4000. Read the data in the transmission buffer memo 1J4000. At this time, if the data sent from the master data processing device is being written to the reception buffer memo 1J4001, the bus 2 is in a low state, so the central control unit 300 controls a portion of the data to be received. After reading the data in the buffer memory 4001 into the main memory unit 301, the data in the transmission buffer memory 1J4000 is transmitted to the master data processing unit.

Next, you can modify some of the transmission data written in the transmission buffer memo U4000 or
We will explain how to read only part of the received data written in the .

The central control unit 300 has a transmission buffer memory 400
23 of the transmission data written in 0, the address of the part to be modified kh' + M buffer memory address address register 4020 should be set (instructed via the control unit 401 IC address bus 304. This address is set in the register 4020. Then, the central control unit 300 controls f.
A read instruction request is issued to the IT unit 401, and the control unit 401
The data at the corresponding address of the transmission buffer memory IJ4t)00 is written to the main memory unit 301K via the data bus 303 under the control of the data bus 303. When it is necessary to modify this partial data, when the central control unit 300 issues a write instruction request to the control unit 401, the control unit 401
From control 9, the modified part molecule is written to the corresponding address of the transmission buffer memory 1J4000 specified by the register 4020. Similarly, the injury buffer memory 4001
Partial data at an arbitrary address within can be read or modified by specifying the address in register 4021.

Furthermore, since the storage capacity of the sending/receiving buffer memo IJ 4000, 4001 is set to the maximum amount of data that can be transferred at one time, as mentioned above, the data transfer from the receiving side is performed after the data transfer from the sending side is completed. Even if the data transfer speeds of the side data processing device and the receiving side data processing device are different, each interface device can have the same hardware configuration.

〔Effect of the invention〕

According to the present invention, the transmitting buffer memory and the receiving buffer memory are provided separately.

Sending or receiving data transfer to other data processing devices.

It becomes possible to simultaneously perform reception or transmission data transfer to the own data processing device. Therefore, high-speed data transfer can be achieved. Also, since the own data processing device can access any address in the transmitting or receiving buffer memory,
It is possible to improve the flexibility of connections between data processing devices, such as partially modifying transmitted data or knowing the nature of all data by reading only a portion of received data. Furthermore, the capacity of the sending and receiving buffer memories is set to the maximum amount of data for one data transfer, so even if the data transfer speeds of each data processing device are different, the interface device can be realized with the same hardware configuration. can.

[Brief explanation of drawings]

Figure 1 is a block diagram of a data processing device equipped with an interface device according to an embodiment of the present invention. Figures 1w1 and 2 are diagrams of a data processing system, and Figure 3 is a block diagram of a data processing device equipped with a conventional interface device. FIG. 41...interface device

Claims (1)

[Claims] 1. In an interface device that is provided in a data processing device and includes a buffer memory and a control unit that controls writing and reading of the buffer memory, one data transfer is performed between the data processing devices as the buffer memory. A transmitting buffer memory and a receiving buffer memory each having a capacity capable of storing a maximum amount of data are provided separately, and an address register for the transmitting buffer memory and an address register for the receiving buffer memory are respectively accessible from the own data processing device. An interface device characterized by being provided with.