JPS57111896A - Locking system of storage device access - Google Patents

Locking system of storage device access

Info

Publication number
JPS57111896A
JPS57111896A JP55187823A JP18782380A JPS57111896A JP S57111896 A JPS57111896 A JP S57111896A JP 55187823 A JP55187823 A JP 55187823A JP 18782380 A JP18782380 A JP 18782380A JP S57111896 A JPS57111896 A JP S57111896A
Authority
JP
Japan
Prior art keywords
locking
given
storage
cpu18
cpu11
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55187823A
Other languages
Japanese (ja)
Other versions
JPS6034144B2 (en
Inventor
Koichi Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55187823A priority Critical patent/JPS6034144B2/en
Publication of JPS57111896A publication Critical patent/JPS57111896A/en
Publication of JPS6034144B2 publication Critical patent/JPS6034144B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Abstract

PURPOSE:To minimize the interruption of access caused by a locking instruction given from a program of another CPU, by using plural processors having buffer storage devices of store through system. CONSTITUTION:In case an access is given to a common region 18 by a program of a CPU11 by means of a locking instruction, the information of a CPU13 is set to a flip-flop circuit and the corresponding data is transferred onto a buffer storage 14. When the CPU11 releases its locking, the contents of the storage 14 corresponding to the address is made ineffective at a CPU18 by a BIC15. Then a locking request is given again when an identification word 16 is fetched from the CPU18. Thus the word 16 is fetched from a main memory 17 with no use of the storage 14, and then set to show that the lock is obtained by itself.
JP55187823A 1980-12-29 1980-12-29 Locking method for storage device access Expired JPS6034144B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55187823A JPS6034144B2 (en) 1980-12-29 1980-12-29 Locking method for storage device access

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55187823A JPS6034144B2 (en) 1980-12-29 1980-12-29 Locking method for storage device access

Publications (2)

Publication Number Publication Date
JPS57111896A true JPS57111896A (en) 1982-07-12
JPS6034144B2 JPS6034144B2 (en) 1985-08-07

Family

ID=16212854

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55187823A Expired JPS6034144B2 (en) 1980-12-29 1980-12-29 Locking method for storage device access

Country Status (1)

Country Link
JP (1) JPS6034144B2 (en)

Also Published As

Publication number Publication date
JPS6034144B2 (en) 1985-08-07

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