JPS57111624A - Priority controlling circuit - Google Patents

Priority controlling circuit

Info

Publication number
JPS57111624A
JPS57111624A JP18822380A JP18822380A JPS57111624A JP S57111624 A JPS57111624 A JP S57111624A JP 18822380 A JP18822380 A JP 18822380A JP 18822380 A JP18822380 A JP 18822380A JP S57111624 A JPS57111624 A JP S57111624A
Authority
JP
Japan
Prior art keywords
ram
selector
signal
address
interruption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18822380A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6152508B2 (enExample
Inventor
Masaki Tsuchiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP18822380A priority Critical patent/JPS57111624A/ja
Publication of JPS57111624A publication Critical patent/JPS57111624A/ja
Publication of JPS6152508B2 publication Critical patent/JPS6152508B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP18822380A 1980-12-27 1980-12-27 Priority controlling circuit Granted JPS57111624A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18822380A JPS57111624A (en) 1980-12-27 1980-12-27 Priority controlling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18822380A JPS57111624A (en) 1980-12-27 1980-12-27 Priority controlling circuit

Publications (2)

Publication Number Publication Date
JPS57111624A true JPS57111624A (en) 1982-07-12
JPS6152508B2 JPS6152508B2 (enExample) 1986-11-13

Family

ID=16219921

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18822380A Granted JPS57111624A (en) 1980-12-27 1980-12-27 Priority controlling circuit

Country Status (1)

Country Link
JP (1) JPS57111624A (enExample)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5556221A (en) * 1978-10-18 1980-04-24 Fujitsu Ltd Priority decision system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5556221A (en) * 1978-10-18 1980-04-24 Fujitsu Ltd Priority decision system

Also Published As

Publication number Publication date
JPS6152508B2 (enExample) 1986-11-13

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