JPS57109081A - Manual switching system of dual-processor system - Google Patents

Manual switching system of dual-processor system

Info

Publication number
JPS57109081A
JPS57109081A JP55188417A JP18841780A JPS57109081A JP S57109081 A JPS57109081 A JP S57109081A JP 55188417 A JP55188417 A JP 55188417A JP 18841780 A JP18841780 A JP 18841780A JP S57109081 A JPS57109081 A JP S57109081A
Authority
JP
Japan
Prior art keywords
switching
switch
cpu
specified
monitoring device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55188417A
Other languages
Japanese (ja)
Other versions
JPS6128147B2 (en
Inventor
Kenji Hiramine
Reijiro Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Tateisi Electronics Co
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tateisi Electronics Co, Omron Tateisi Electronics Co filed Critical Tateisi Electronics Co
Priority to JP55188417A priority Critical patent/JPS57109081A/en
Publication of JPS57109081A publication Critical patent/JPS57109081A/en
Publication of JPS6128147B2 publication Critical patent/JPS6128147B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)

Abstract

PURPOSE:To prevent switching due to malfunction and to switch CPUs only when prescribed switching operation is performed, by providing a switching specifying switch with which processors are specified and a push button switch for the confirmation of switching. CONSTITUTION:An in-use a stand-by CPU, memories, input-output equipments, etc., are connected internal buses 37 and 38 respectively, and a bus switching gate 42 is connected to both the buses 37 and 38. Further, the buses 37 and 38 are connected to a monitoring device 41 through timers T1 and T2, and the switching gate 42 is controlled by the output of the monitoring device 41 to connect said in-use and stand-by CPUs to a external switching bus 39. The CPU to be connected is specified by the switching setting switch 44 of the monitoring device 41, and the switching is confirmed with a push button switch 43 for confirmation. As far as the switch 43 is pressed for a constant time, the CPU specified with the setting switch 44 is connected to the external bus 39 to prevent switching due to malfunction.
JP55188417A 1980-12-26 1980-12-26 Manual switching system of dual-processor system Granted JPS57109081A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55188417A JPS57109081A (en) 1980-12-26 1980-12-26 Manual switching system of dual-processor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55188417A JPS57109081A (en) 1980-12-26 1980-12-26 Manual switching system of dual-processor system

Publications (2)

Publication Number Publication Date
JPS57109081A true JPS57109081A (en) 1982-07-07
JPS6128147B2 JPS6128147B2 (en) 1986-06-28

Family

ID=16223291

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55188417A Granted JPS57109081A (en) 1980-12-26 1980-12-26 Manual switching system of dual-processor system

Country Status (1)

Country Link
JP (1) JPS57109081A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61133465A (en) * 1984-11-30 1986-06-20 Seiko Epson Corp Switching method of cpu
JPS61221941A (en) * 1985-03-28 1986-10-02 Toshiba Corp Back up device for programmable controller

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0514352Y2 (en) * 1985-03-05 1993-04-16

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61133465A (en) * 1984-11-30 1986-06-20 Seiko Epson Corp Switching method of cpu
JPS61221941A (en) * 1985-03-28 1986-10-02 Toshiba Corp Back up device for programmable controller

Also Published As

Publication number Publication date
JPS6128147B2 (en) 1986-06-28

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