JPS5775336A - Separating system of faulty device - Google Patents

Separating system of faulty device

Info

Publication number
JPS5775336A
JPS5775336A JP55151092A JP15109280A JPS5775336A JP S5775336 A JPS5775336 A JP S5775336A JP 55151092 A JP55151092 A JP 55151092A JP 15109280 A JP15109280 A JP 15109280A JP S5775336 A JPS5775336 A JP S5775336A
Authority
JP
Japan
Prior art keywords
devices
common bus
controlled
processor cpu
faulty device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55151092A
Other languages
Japanese (ja)
Inventor
Shigenori Sakai
Taro Yokoyama
Hisao Kono
Masaaki Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55151092A priority Critical patent/JPS5775336A/en
Publication of JPS5775336A publication Critical patent/JPS5775336A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To completely disconnect a faulty device, by cutting off all devices to be controlled from a common bus while the signal which separates the faulty device is flowing to the common bus and accordingly preventing the transmission of noise to the common bus. CONSTITUTION:When a processor CPU detects that a fault arises at one of devices X1-Xn to be controlled, e.g., the device X1, the processor CPU sends a command to a non-individual controller F to set the corresponding flip-flop. With the output of the flip-flop, switches SW12-SWn2 are all cut off at a time and then controlled. As a result, all devices X1-Xn are cut off at a time from a common bus B. The processor CPU transmits the information to an individual controller Y to connect all nondefect devices X2-Xn to the bus B excepting for the favlty device X1.
JP55151092A 1980-10-28 1980-10-28 Separating system of faulty device Pending JPS5775336A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55151092A JPS5775336A (en) 1980-10-28 1980-10-28 Separating system of faulty device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55151092A JPS5775336A (en) 1980-10-28 1980-10-28 Separating system of faulty device

Publications (1)

Publication Number Publication Date
JPS5775336A true JPS5775336A (en) 1982-05-11

Family

ID=15511152

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55151092A Pending JPS5775336A (en) 1980-10-28 1980-10-28 Separating system of faulty device

Country Status (1)

Country Link
JP (1) JPS5775336A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59160900A (en) * 1982-12-20 1984-09-11 テキサス・インスツルメンツ・インコ−ポレイテツド Electronic device system
JPS60198637A (en) * 1984-03-22 1985-10-08 Shimadzu Corp Constitution control system
JP2009217435A (en) * 2008-03-10 2009-09-24 Fujitsu Ltd Control method, information processing apparatus, and storage system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59160900A (en) * 1982-12-20 1984-09-11 テキサス・インスツルメンツ・インコ−ポレイテツド Electronic device system
JPS60198637A (en) * 1984-03-22 1985-10-08 Shimadzu Corp Constitution control system
JPH0533415B2 (en) * 1984-03-22 1993-05-19 Shimadzu Corp
JP2009217435A (en) * 2008-03-10 2009-09-24 Fujitsu Ltd Control method, information processing apparatus, and storage system
JP4644720B2 (en) * 2008-03-10 2011-03-02 富士通株式会社 Control method, information processing apparatus, and storage system

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