JPS57108951A - Memory busy control system - Google Patents

Memory busy control system

Info

Publication number
JPS57108951A
JPS57108951A JP18611080A JP18611080A JPS57108951A JP S57108951 A JPS57108951 A JP S57108951A JP 18611080 A JP18611080 A JP 18611080A JP 18611080 A JP18611080 A JP 18611080A JP S57108951 A JPS57108951 A JP S57108951A
Authority
JP
Japan
Prior art keywords
access
port
vector unit
main storage
request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18611080A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6218063B2 (enrdf_load_stackoverflow
Inventor
Mikio Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18611080A priority Critical patent/JPS57108951A/ja
Publication of JPS57108951A publication Critical patent/JPS57108951A/ja
Publication of JPS6218063B2 publication Critical patent/JPS6218063B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)
JP18611080A 1980-12-25 1980-12-25 Memory busy control system Granted JPS57108951A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18611080A JPS57108951A (en) 1980-12-25 1980-12-25 Memory busy control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18611080A JPS57108951A (en) 1980-12-25 1980-12-25 Memory busy control system

Publications (2)

Publication Number Publication Date
JPS57108951A true JPS57108951A (en) 1982-07-07
JPS6218063B2 JPS6218063B2 (enrdf_load_stackoverflow) 1987-04-21

Family

ID=16182529

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18611080A Granted JPS57108951A (en) 1980-12-25 1980-12-25 Memory busy control system

Country Status (1)

Country Link
JP (1) JPS57108951A (enrdf_load_stackoverflow)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4538056A (en) * 1982-08-27 1985-08-27 Figgie International, Inc. Card reader for time and attendance
US4544832A (en) * 1982-08-27 1985-10-01 Figgie International, Inc. Card reader with buffer for degraded mode
JPS61161565A (ja) * 1985-01-11 1986-07-22 Nec Corp 記憶装置
JPS61239341A (ja) * 1985-04-16 1986-10-24 Fujitsu Ltd メモリビジ−チエツク方式
JPS63100552A (ja) * 1986-10-17 1988-05-02 Nec Corp メモリアクセス制御方式
US4816658A (en) * 1983-01-10 1989-03-28 Casi-Rusco, Inc. Card reader for security system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4966035A (enrdf_load_stackoverflow) * 1972-10-30 1974-06-26

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4966035A (enrdf_load_stackoverflow) * 1972-10-30 1974-06-26

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4538056A (en) * 1982-08-27 1985-08-27 Figgie International, Inc. Card reader for time and attendance
US4544832A (en) * 1982-08-27 1985-10-01 Figgie International, Inc. Card reader with buffer for degraded mode
US4816658A (en) * 1983-01-10 1989-03-28 Casi-Rusco, Inc. Card reader for security system
JPS61161565A (ja) * 1985-01-11 1986-07-22 Nec Corp 記憶装置
JPS61239341A (ja) * 1985-04-16 1986-10-24 Fujitsu Ltd メモリビジ−チエツク方式
JPS63100552A (ja) * 1986-10-17 1988-05-02 Nec Corp メモリアクセス制御方式

Also Published As

Publication number Publication date
JPS6218063B2 (enrdf_load_stackoverflow) 1987-04-21

Similar Documents

Publication Publication Date Title
JPS57189231A (en) Data transferring system
JPS57108951A (en) Memory busy control system
EP0309330A3 (en) Access priority control system for main storage for computer
CA1273713C (en) VECTOR PROCESSING SYSTEM
JPS5783843A (en) Data buffer controlling system
JPS57108952A (en) Busy control system
JPS56169281A (en) Data processor
JPS56157518A (en) Communication device between processing devices
JPS5783839A (en) Control system for interruption request priority
JPS57153328A (en) Terminal device with keying data pushup storage function
JPS56143583A (en) Buffer memory control system
JPS576480A (en) Buffer memory control system
JPS5725053A (en) Memory device
JPS5724085A (en) Information process system
JPS5730169A (en) Cash memory control system
JPS56129473A (en) Facsimile device with memory device
JPS57150017A (en) Direct memory access system
JPS5348433A (en) Precedence control system
JPS54129941A (en) Cross-call control system
JPS5535572A (en) Storage exchange system
JPS57143956A (en) Mutual communication system between half duplex and full duplex terminal
JPS56107691A (en) Trunk selective system
JPS5714931A (en) Interruption controlling system
KR880014450A (ko) 리얼타임데이타 입출력장치
JPS5566015A (en) Shared line state detection system