JPS57108680A - Radar signal processor - Google Patents
Radar signal processorInfo
- Publication number
- JPS57108680A JPS57108680A JP55184253A JP18425380A JPS57108680A JP S57108680 A JPS57108680 A JP S57108680A JP 55184253 A JP55184253 A JP 55184253A JP 18425380 A JP18425380 A JP 18425380A JP S57108680 A JPS57108680 A JP S57108680A
- Authority
- JP
- Japan
- Prior art keywords
- radar
- output
- radar video
- memory
- video signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/28—Details of pulse systems
- G01S7/285—Receivers
- G01S7/295—Means for transforming co-ordinates or for evaluating data, e.g. using computers
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Radar Systems Or Details Thereof (AREA)
Abstract
PURPOSE:To enable the renewal of a radar video memory in non-sychronization with a PPI sweep by memorizing and reading a radar video synchronizing a raster scanning with a first in/first out memory. CONSTITUTION:A digitalized video signal output from a radar signal synchronization circuit to respective input terminals I of first in/first out buffer registers 12a and 12b. This input timing is controlled by clock pulses RCKA and RCKB varied in the phase fed to respective input clock terminals LCK. With the feeding of clock pulses CACKA and CAZCKB varied in the phase to an output clock terminal OCK, a radar video signal is output from an output terminal 0, synthesized with an OR circuit 12c and written into a video memory. This enables the cycle conversion of the radar video signal at a high speed thereby allowing the renewal of the radar video memory in non-synchronization with a PPI sweep.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55184253A JPS57108680A (en) | 1980-12-25 | 1980-12-25 | Radar signal processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55184253A JPS57108680A (en) | 1980-12-25 | 1980-12-25 | Radar signal processor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57108680A true JPS57108680A (en) | 1982-07-06 |
Family
ID=16150068
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55184253A Pending JPS57108680A (en) | 1980-12-25 | 1980-12-25 | Radar signal processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57108680A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02226082A (en) * | 1989-02-27 | 1990-09-07 | Tokyo Keiki Co Ltd | Radar display unit |
-
1980
- 1980-12-25 JP JP55184253A patent/JPS57108680A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02226082A (en) * | 1989-02-27 | 1990-09-07 | Tokyo Keiki Co Ltd | Radar display unit |
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