EP0244991A3 - Variable delay circuit - Google Patents

Variable delay circuit Download PDF

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Publication number
EP0244991A3
EP0244991A3 EP87303608A EP87303608A EP0244991A3 EP 0244991 A3 EP0244991 A3 EP 0244991A3 EP 87303608 A EP87303608 A EP 87303608A EP 87303608 A EP87303608 A EP 87303608A EP 0244991 A3 EP0244991 A3 EP 0244991A3
Authority
EP
European Patent Office
Prior art keywords
display terminal
processing unit
synchronisation signals
delay circuit
variable delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP87303608A
Other languages
German (de)
French (fr)
Other versions
EP0244991A2 (en
Inventor
Richard James Humpleman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AMT Holdings Ltd
Original Assignee
AMT Holdings Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AMT Holdings Ltd filed Critical AMT Holdings Ltd
Publication of EP0244991A2 publication Critical patent/EP0244991A2/en
Publication of EP0244991A3 publication Critical patent/EP0244991A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/12—Synchronisation between the display unit and other units, e.g. other display units, video-disc players

Abstract

A data processing system is described comprising a display terminal (10) and a processing unit (11). The display terminal includes a video timing generator (14) producing synchronisation signals (VSYNC, HSYNC). This triggers requests (QUAL) for the processing unit to supply video data. The display terminal includes a variable delay circuit (24) which measures the time delay between the outgoing request and the incoming data, and causes the synchronisation signals to be delayed by a corresponding amount. This ensures that the synchronisation signals are maintained in the correct timing relationship with the video data, irrespective of any unknown delays between the display terminal and the processing unit.
EP87303608A 1986-05-03 1987-04-24 Variable delay circuit Withdrawn EP0244991A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB868610888A GB8610888D0 (en) 1986-05-03 1986-05-03 Variable delay circuit
GB8610888 1986-05-03

Publications (2)

Publication Number Publication Date
EP0244991A2 EP0244991A2 (en) 1987-11-11
EP0244991A3 true EP0244991A3 (en) 1989-10-18

Family

ID=10597319

Family Applications (1)

Application Number Title Priority Date Filing Date
EP87303608A Withdrawn EP0244991A3 (en) 1986-05-03 1987-04-24 Variable delay circuit

Country Status (2)

Country Link
EP (1) EP0244991A3 (en)
GB (1) GB8610888D0 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES2713418T3 (en) 2016-05-13 2019-05-21 Oreal Device for treating hair and related procedure

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3887769A (en) * 1973-04-04 1975-06-03 Bell Telephone Labor Inc Frame syncrhonization of elastic data bit stores
GB2073515A (en) * 1980-04-04 1981-10-14 Int Standard Electric Corp Frequency locked loop
GB2128450A (en) * 1982-10-04 1984-04-26 Hitachi Ltd Time-division switching unit
EP0175564A2 (en) * 1984-09-21 1986-03-26 Amt(Holdings) Limited Data transfer system
EP0180450A2 (en) * 1984-10-31 1986-05-07 Rca Licensing Corporation Television display apparatus having character generator with non-line-locked clock

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5630369A (en) * 1979-08-20 1981-03-26 Toshiba Corp Audio signal delay compensator
JPS59216334A (en) * 1983-05-24 1984-12-06 Nippon Telegr & Teleph Corp <Ntt> Adjusting system of multistation control signal timing

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3887769A (en) * 1973-04-04 1975-06-03 Bell Telephone Labor Inc Frame syncrhonization of elastic data bit stores
GB2073515A (en) * 1980-04-04 1981-10-14 Int Standard Electric Corp Frequency locked loop
GB2128450A (en) * 1982-10-04 1984-04-26 Hitachi Ltd Time-division switching unit
EP0175564A2 (en) * 1984-09-21 1986-03-26 Amt(Holdings) Limited Data transfer system
EP0180450A2 (en) * 1984-10-31 1986-05-07 Rca Licensing Corporation Television display apparatus having character generator with non-line-locked clock

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 5, no. 82 (E-59)(754) 29 May 1981; & JP-A-56 030 369 (TOKYO SHIBAURA DENKI K.K.) 26.03.1981 *
PATENT ABSTRACTS OF JAPAN vol. 9, no. 85 (E-308)(1808) 13 April 1985; & JP-A-59 216 334 (NIPPON DENSHIN DENWA KOSHA) 06.12.1984 *

Also Published As

Publication number Publication date
GB8610888D0 (en) 1986-06-11
EP0244991A2 (en) 1987-11-11

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Inventor name: HUMPLEMAN, RICHARD JAMES