JPS57168550A - Processing system of pcm receiving data - Google Patents

Processing system of pcm receiving data

Info

Publication number
JPS57168550A
JPS57168550A JP56053848A JP5384881A JPS57168550A JP S57168550 A JPS57168550 A JP S57168550A JP 56053848 A JP56053848 A JP 56053848A JP 5384881 A JP5384881 A JP 5384881A JP S57168550 A JPS57168550 A JP S57168550A
Authority
JP
Japan
Prior art keywords
frame
receiving data
signal
register
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56053848A
Other languages
Japanese (ja)
Inventor
Toshiyuki Tsurumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56053848A priority Critical patent/JPS57168550A/en
Publication of JPS57168550A publication Critical patent/JPS57168550A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/08—Speed or phase control by synchronisation signals the synchronisation signals recurring cyclically

Abstract

PURPOSE:To process the data which is so far defined ineffective as an effective data, by using a buffer register having an (N-1)-fold length of the frame that stores the receiving data and validating the output of the stored receiving data at and after the establishment of frame synchronization. CONSTITUTION:In the case of the frame synchronizing signal where N=2, the receiving data A given from a receiver 1 is stored in a 1-frame buffer register 4, and the output receiving data B is delivered with a delay of a frame. The frame synchronizing signal D given from the receiver 1 is supplied to a shift register 5 and an OR circuit 7 in the form of a signal E having a delay of a frame. As a result, the output G of the circuit 7 is delivered as a signal which is longer than the signal D by a frame. Receiving the signal G, an AND circuit 6 feeds the reset signal F to a register 4 to reset the register. Thus the register 4 starts the stroage of the receiving data and then starts the output with a delay equivalent to the 1-frame length given to the receiving data. Then the frame synchronization is established with receiving data b and c.
JP56053848A 1981-04-10 1981-04-10 Processing system of pcm receiving data Pending JPS57168550A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56053848A JPS57168550A (en) 1981-04-10 1981-04-10 Processing system of pcm receiving data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56053848A JPS57168550A (en) 1981-04-10 1981-04-10 Processing system of pcm receiving data

Publications (1)

Publication Number Publication Date
JPS57168550A true JPS57168550A (en) 1982-10-16

Family

ID=12954182

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56053848A Pending JPS57168550A (en) 1981-04-10 1981-04-10 Processing system of pcm receiving data

Country Status (1)

Country Link
JP (1) JPS57168550A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59185452A (en) * 1983-04-06 1984-10-22 Fujitsu Ltd Discarding system of initial illegal information
JPS6490628A (en) * 1987-09-30 1989-04-07 Iwatsu Electric Co Ltd Terminal equipment
JPH0193226A (en) * 1987-10-03 1989-04-12 Iwatsu Electric Co Ltd Terminating device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59185452A (en) * 1983-04-06 1984-10-22 Fujitsu Ltd Discarding system of initial illegal information
JPS6490628A (en) * 1987-09-30 1989-04-07 Iwatsu Electric Co Ltd Terminal equipment
JPH0193226A (en) * 1987-10-03 1989-04-12 Iwatsu Electric Co Ltd Terminating device

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