JPS6430345A - Synchronizing detecting circuit - Google Patents

Synchronizing detecting circuit

Info

Publication number
JPS6430345A
JPS6430345A JP62185389A JP18538987A JPS6430345A JP S6430345 A JPS6430345 A JP S6430345A JP 62185389 A JP62185389 A JP 62185389A JP 18538987 A JP18538987 A JP 18538987A JP S6430345 A JPS6430345 A JP S6430345A
Authority
JP
Japan
Prior art keywords
circuit
serial data
frame
frame length
ram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62185389A
Other languages
Japanese (ja)
Inventor
Akihiko Kunihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62185389A priority Critical patent/JPS6430345A/en
Publication of JPS6430345A publication Critical patent/JPS6430345A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To cause the frame length of input data to be variable and to simplify a circuit by using a RAM, to which an address is supplied from a counter having an automatic initial value resetting function, for detecting a frame bit pattern. CONSTITUTION:A circuit 5 is provided which supplies the address from a counter, in which the frame period of serial data is set, to a RAM 3, and detects the frame bit pattern by fetching data separated for the frame length on the serial data in the sequence of adjoining bits on the same address, and by changing the period of the counter 1, the frame length of the serial data is made to be variable. In such a way, by using a RAM 3 instead of plural shift registers, a correspondence to the frame length of variable serial data can be made possible, and since the number of elements to be used can be reduced, a circuit constitution can be simplified, and the circuit can be miniaturized.
JP62185389A 1987-07-27 1987-07-27 Synchronizing detecting circuit Pending JPS6430345A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62185389A JPS6430345A (en) 1987-07-27 1987-07-27 Synchronizing detecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62185389A JPS6430345A (en) 1987-07-27 1987-07-27 Synchronizing detecting circuit

Publications (1)

Publication Number Publication Date
JPS6430345A true JPS6430345A (en) 1989-02-01

Family

ID=16169954

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62185389A Pending JPS6430345A (en) 1987-07-27 1987-07-27 Synchronizing detecting circuit

Country Status (1)

Country Link
JP (1) JPS6430345A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5030512A (en) * 1989-09-20 1991-07-09 International Business Machines Corporation Magneto-optical recording medium

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5030512A (en) * 1989-09-20 1991-07-09 International Business Machines Corporation Magneto-optical recording medium

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