GB2073515A

GB2073515A - Frequency locked loop

Info

Publication number: GB2073515A
Application number: GB8109161A
Authority: GB
Original assignee: International Standard Electric Corp
Current assignee: International Standard Electric Corp
Priority date: 1980-04-04
Filing date: 1981-03-24
Publication date: 1981-10-14
Also published as: GB2073515B; BE888265A; FR2480048A1

Abstract

A frequency-locked analog loop having a high degree of frequency stability includes a phase-locked loop comprising a phase comparator (1), a low-pass filter (2) and a voltage-controlled oscillator (3) from which the output di is derived. The phase-locked loop also includes a multiplexer (4) with a step-adjustable delay line (5) so that any out-of-phase condition detected by the comparator (1) adjusts the phase of the signal in the loop. The delay introduced (4, 5) is controlled by an up-down counter (9), a phase-shift detector (8) and the phase comparator (1) output so as to compensate any phase shift in the input signal without appreciable variation of the oscillator frequency. This phase shift control circuit operates with a shorter time constant than the loop and is enabled by a lock detector 10 only in the synchronised state of the loop. <IMAGE>

Description

SPECIFICATION Frequency locked loop This invention relates to a frequency-locked analog loop containing a phase-locked loop including a phase comparator which receives an in put signal çi and a loop output signal cpl, a low-pass filter and a voltage-controlled oscillator (VCO), furnishing the output signal coo, the loop output signal cpl being derived from the output signal cpo.

It is common practice to lock the frequency of an output signal to the frequency of an input signal by a phase-locked loop. The phase comparator of such a loop gives an indication of a phase difference, between the input and output signals, by detecting the appearance of a phase shift. The signal from the comparator, after passing through a low-pass filter, acts on the oscillator frequency to correct this difference. When such a loop is locked, any phase shift of the input signal varies the oscillator frequency to compensate for this phase shift, so that a variation in the phase of the input signal is accompanied by a variation in output frequency.

Such behaviour can be a problem in some~cases.

Thus, in PCM telephone exchanges, the master clock is duplicated for operational security, two master clocks being used, which have the same frequency but whose phases are not locked together. These clocks supply local clock signals to the various units of the exchange. If, for example, due to the failure of one clock or for maintenance purposes, we switch from one clock to the other, at the level of the units of the exchange and particularly those receiving signals from the junctions coming into the exchange, the frequency variation due to the use of a conventional phase-locked loop to compensate for any phase shift, appears as a loss of synchronisation triggering a resynchronisation process which may cause a loss in the message. For some types of messages, this constitutes a serious problem.

An object of the invention is therefore a frequency-locked analog loop which, in case of the phase shift of the input signal, permits the momentary frequency variation of the output signal to be kept below a predetermined minimum value.

According to the invention there is provided a frequency-locked analog loop containing aphase- locked loop, in which the phase-locked loop includes a phase comparator which comprises at its input a signal cpi and a loop output signal cpl, a low-pass filter and a voltage-controlled oscillator which supplies an output signal cpo, in which the signal fl is the loop output signal and is derived from the output signal cpo, in which the frequency-locked analog loop also includes variable delay means for obtaining the signal cpl by applying a variable delay to the signal fO, and in which the loop also includes controlling means for controlling the value of the delay applied by said variable delay means, in response to signals furnished by the phase comparator, so as to reduce any phase shift indicated by the said comparator.

Since the response time of the said means is much shorter than the time constant of the low-pass filter of the loop, the phase shift of the input signal is almost completely compensated, without requiring a large variation in the oscillator frequency.

An embodiment of the invention will now be described with reference to the attached drawings, in which: Figure lisa block diagram of a frequency-locked analog loop embodying the invention; Figure 2 shows some explanatory signal waveforms; and Figure 3 is a more detailed representation of the circuit of Figure 1.

In figure 1, we find the conventional elements of a phase-locked loop, namely a phase comparator 1, a low-pass filter 2 and a voltage-controlled oscillator (VCO) 3. To obtain, at the output, an output signal ço with a well defined on-off ratio, we use an oscillator 3 operating at twice the frequency of the input signal cpi and a divide-by-two divider 7. This provides an output signal to having the same frequency as that of the input signal and with a well defined on-off ratio. Another divide-by-two divider 6 is included in the loop.

A delay line 5 and a multiplexer4 are placed in the loop, between the output of oscillator 3 and the second input of the phase comparator 1, to which the loop output signal fl is applied. Thus one can choose either the output signal from oscillator 3 applied directly, or one of the uniformly spaced output signals from the delay line. This permits a variable delay to be applied to the signal from oscillator 3 to provide the signal cpl. The multiplexer 4 is controlled by a control circuit including an up/down counter 9 and a phase-shifter detector 8.The latter determines, from signals supplied by the phase comparator 1, whether a phase shift of the input signal cpi exists and in what direction, and commands the up/down counter to count up or down so as to select an output of multiplexer 4 which will reduce the phase shift indicated by the phase comparator 1. In addition, a lock detector circuit 10 inhibits the operation of the control circuit when the loop is not locked.

The operation of the system is now explained with reference also to figure 2. It will be assumed, as an example, that the signal cpi has a frequency of 8 MHz, so that the VCO 3 operates at 16 MHz. The delay line 5 has with five outputs, uniformly spaced by 10 nanoseconds, the first output being delayed itself by ten nanoseconds with respect to the output of oscillator 3. Any phase shift on the input signal (oi can thus be compensated, in steps of ten nanoseconds, with the six inputs of the multiplexer providing for a shift of one complete cycle of the signal of oscillator 3. The residual phase shift, for which the oscillator 3 must compensate by varying its frequency, cannot therefore be greater than ten nanoseconds. An output signal cpo of very stable frequency is thus obtained.Figure 2 shows the phase relationships of the circuit, with signals çi and çl being in phase. It is assumed that when in balance after locking, it was the inputs of the multiplexerthat had been selected.

The signalsf16.0to f16.5 are those which exist at inputs 0 to 5 ofthe multiplexer4, with the phase shift r, between two successive inputs, being equal to ten nanoseconds.

The lock detector circuit 10 prevents the multiplexer from being commanded continually and jumping from one input to another during the loop acquisition period when the frequency of oscillator 3 is not yet locked to the frequency of the input signal cpi.

Figure 3 shows the frequency-locked analog loop of figure 1, with the various blocks of figure 1 drawn with dashed lines when their components are shown in detail. The phase comparator lisa digital com paratorwhich gives, atone orthe otherofthe out putsup anddwofflip-flops 11 and 12, pulses whose lengths are proportional to the phase shift between the signals wi and (awl, when the signal cpi leads or lags signal vl respectively.These pulses are applied to the filter 2 constructed, in the known way, of a socalled "charge pump" circuit, with two diodes 26,28 and two resistors 27,29, connected to the input of an integrator containing an operational amplifier 20, a capacitor 22 and resistors 21, 23, 24, 25. The integrator output signal controls the VCO 3. The phaseshift detector 8 consists of two NAND gates 81 and 82 with three in puts, receiving respectively the enable signal from the lock detector 10, the positive pulses from the flip-flops 11 and 12, and the same pulses delayed by inverters 83,84 and 85,86 respectively. The outputs of NAND gates 81 and 82 pass count-down and count-up pulses respectively to the count-down input CDW and to the count-down and count-up pulses respectively to the count-down input CDW and to the count-up input CUP of the up/down counter 9 having a capacity of six.This counter furnishes, at its three outputs, the three control bits to the multiplexer 4. The lock detector 10 contains an integrating circuit including a resistor 103, a capacitor 104 and an analog voltage comparator 105, a NAND gate 101 and an inverter 102.

The inputs of the NAND gate 101 are connected to the inverted outputs Q of fl ip-flops 11 and 12.

The operation ofthe circuit will be explained below with reference to certain waveforms shown in figure 2.

The known phase comparator 1 contains two J-K flip-flops 11 and 12, whose outputs are changed on a change from the high level to the iow level at the clock inputCK, provided thatthe signal at the reset inputCLR is atthe high level. If the signals and cpl are in phase,flip-flops 11 and 12 remain constantly at 0, which keeps the diodes 26 and 28 cut off. The integrator of filter 2 furnishes a constant signal which maintains the frequency of the oscillator 3 constant. No pulse is supplied to circuit 8, and the content of the counter 9 remains constant. The multiplexer 4 remains on the selected input (0, in this case) and this gives a signal cpl in phase with the input signal fi.

If the input signal wi undergoes a phase shift so that it lags by a time t1 (signals in figure 2 for the case "phase lag"), the flip-flop 12 gives pulses at the output dw. Since it is assumed that the loop is locked, circuit 10 furnishing a high level, the pulses at output dw will be transmitted inverted by gate 82 and with a trailing edge delayed, with respect to the rising edge of the pulses at output dw, by a predetermined time equal to the delay introduced by the two inverters 85 and 86. In figure 2, we have shown the signal dw present at the output Q of flipflop 12 and which is identical to the pulses from gate 82 to the count-up input CUP, except for the position of the falling edge which should be delayed by the delay mentioned above.We see that these pulses at the count-up input CUP permit a jump from one input of the multiplexer 4 to the next lagging input, on each cycle of the signal cpl. The jump from input 0 to input 1 is shown in figure 2. These jumps continue as long as the phase shift, between the signal cpi and the shifted signal cpl, remains greater than a value corresponding to one pulse length at the output dw greater than the delay due to the inverter 85 and 86.

This delay is such that only pulses longerthan 10 nanoseconds can trigger the up/down counter 9.

Thus, at the end of a certain number of cycles corresponding to the accumulated phase shift of signal ç I compensating, to within 10 nanoseconds, for the phase shift of the signal çi, the compensation circuit returns to its position of balance. The total time for this compensating operation is much less than the time constant of the integrator of filter 2 (which is, for example, around 100 ms).Thus, oscillator 3 is controlled, through filter 2, by the residual pulses at the outputdw, of a duration of less than 10 nanoseconds, and its frequency thus varies very little to bring the signals cpi and ç I into phase.

Figure 2 also shows signals for a case in which the signal wi develops a phase lead by an amountt2 with respect to signal cpl. As before, the pulses at the phase comparator output up are identical to those from gate 81 to the count-down input CDW, except that the falling edge is delayed by inverters 83 and 84. Figure 2 shows two successive jumps of multip lexer 4, from input 0 to input5 and then from input 5 to input 4. Of course,the counter9 is designed to changed from the code 000 to the code 101, in this example, when it receives a pulse at its countdpwn input.

The lock detector circuit 10 contains a NAND gate 101, whose inputs are connected to the inverse outputs Q of flipflops 11 and 12, followed by an inverter 102. When the loop is locked, and in the absence of phase shift, capacitor 104 is charged to the High level because no pulses are furnished by flip-flops 11 and 12. A high level, enabling the operation of circuit 8, is the present at the corresponding inputs of the NAND gates 81 and 82. The integration time constant of circuit 10 is made long enough, preferably longer than the loop acquisition period, for the pulses from the comparator, in case of a phase shift, to be unable to appreciably vary the level of the output signal. On the other hand, during the loop acquisition period, capacitor 104 cannot charge up to the high level due to the repeated pulses supplied by phase comparator 1.

Claims

1. Afrequency-locked analog loop containing a phase-locked loop, in which the phase-locked loop includes a phase comparator, which comprises at its input a signal cpi and a loop output signal cpl, a lowpass filter and a voltage-controlled oscillator which supplies an output signal cpo, in which the signal cpl is the loop output signal and is derived from the output signal cpo, in which the frequency-locked analog loop also includes variable delay means for obtaining the signal cpl by applying a variable delay to the signal cpo, and in which the loop also includes controlling means for controlling the value of the delay applied by said variable delay means, in response to signals furnished by the phase comparator, so as to reduce any phase shift indicated by the said comparator.

2. An analog loop according to claim 1, and in which said variable delay means include a multiplexer, one input of which receives the signal ço directly, and a delay line the input of which receives the signal cpo and which has several uniformly spaced outputs connected respectively to the other inputs of the multiplexer which connects one of its inputs to its output under the control of the said controlling means.

3. An analog loop according to claim 1 or 2, and in which said controlling means includes a phaseshift detector which detects the appearance of a phase shift between signals çi and cpl, and an up/down counterwhich counts up or down under the control of the phase-shift detector, the digital output of which controls the said multiplexer, the counting capacity of the upldown counter being equal to the number of multiplexer inputs.

4. An analog loop according to claims 1,2 or 3, and in which said controlling means also include a lock detector circuit receiving the output signals from the phase comparator and enabling the operation of the said controlling means only when the loop is locked.

5. An analog loop according to claim 3 or4 as appended to claim 3, in which the phase comparator is a digital phase comparator which gives a first output commanding, through the filter, an increase in the oscillator frequency when the signal cpi is leading the signal cpl, or a second output commanding a decrease in the oscillator frequency when the signal cpi is lagging the signal fl, the duration of the pulses on the first or the second output being proportional to the phase shift between the signals çi and (al, in which said phase-shift detector includes means to transmit the pulses of the first output to the countdown input of the up/down counter, and in which the pulses of the second output are applied to the count-up input of the counter, provided that the said pulses have a minimum predetermined length and that the lock detector furnishes an enable signal indicating that the loop is locked.

6. An analog loop according to claim 5, in which said means for transmitting the pulses include two NAND gates, whose outputs are connected respec timely to the count-down input and the count-up input of the counter, and each of which includes three inputs receiving respectively the enable signal, the pulses of the corresponding output of the phase comparator and these same pulses delayed by the said predetermined time by the delay circuits.

7. An analog loop according to claim 5 or 6, in which said lock detector circuit includes gate circuit receiving the output signals from the phase comparator, and an integrating circuit connected to the output of the gate circuit and furnishing the enable signal, with the time constant of the integrating circuit being made longer than the normal loop acquisition time.

8. An analog loop according to any preceding claim and in which the voltage-controlled oscillator has a frequency equal to n times that of the input signal cpi, and in which divide-by-n frequency dividers are provided to furnish the loop output signal cpl and the output signal cpo, from the oscillator output signal.

9. An analog loop according to claim 8, and in which the number n is equal to two, the divide-bytwo dividers consisting of flip-flops of the JK type.

10. Afrequency-locked analog loop, substantially as described with reference to the accompanying drawings.

New claims or amendments to claims filed on 28 May 1981 New or amended claims:- New claim 11

11. A frequency-locked analog loop circuit con- taining a phase-locked loop, in which the phaselocked loop includes a phase comparator followed by a low-pass filter and a voltage-controlled oscillator from which the output of the circuit is derived, in which the comparator compares an input signal ;; with a further signal Oi derived from the output of the voltage-controlled oscillator, in which the outputs obtained from the comparator are applied to the voltage controlled oscillator via the low pass filter in such a way as to vary the output frequency and phase of that oscillator, in which the phase-locked loop includes a variable delay device to which the output of the oscillator is applied, the output of the variable delay device providing said further signal IZI, which is thus derived from the oscillator by the application to that output of a variable delay, in which the output signals from the phase comparator, which indicate the extent of the phase difference (if any) between the input signal 0 and the further signal said are applied to a control circuit for said variable delay circuit, such that said control circuit so adjusts said delay circuit as to reduce the phase difference between the input signals Oi and the further signal IZI,, thus varying the output applied to the voltage controlled oscillator in such a way as to tend to synchronise the output of the circuit with the input signal Pli.