JPS5530789A - Video display device - Google Patents

Video display device

Info

Publication number
JPS5530789A
JPS5530789A JP10405878A JP10405878A JPS5530789A JP S5530789 A JPS5530789 A JP S5530789A JP 10405878 A JP10405878 A JP 10405878A JP 10405878 A JP10405878 A JP 10405878A JP S5530789 A JPS5530789 A JP S5530789A
Authority
JP
Japan
Prior art keywords
output
cpu
display
microcomputer
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10405878A
Other languages
Japanese (ja)
Other versions
JPS6217767B2 (en
Inventor
Akira Usui
Yoshio Yasumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP10405878A priority Critical patent/JPS5530789A/en
Publication of JPS5530789A publication Critical patent/JPS5530789A/en
Publication of JPS6217767B2 publication Critical patent/JPS6217767B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Digital Computer Display Output (AREA)

Abstract

PURPOSE: To make it possible to display video on CRT easily even in case display data are made to output from CPU which the microcomputer of low clock frequency is used, by mounting the changeover pulse generation unit.
CONSTITUTION: Output of the oscillator 9 having frequency of approx. "n" times as high as the horizontal synchronizing signal which is input from the line E has output terminals of "n" pieces, and is added to the changeover pulse generation unit 10 such as a ring counter which generates output in order from the first output terminal to the n-th one whenever 1 bit of the oscillation 9 output is generated. On the other hand, the output terminals of the output port 11 of CPU 5 consisting of a microcomputer, etc. are mounted by "n" pieces, as well, which take the logical product 12 of each bit of each output terminal of the above CPU 5 and the unit 10, its output is compounded by OR gate 13, and the video signal for display is output from the data bus C. Also, as for the display data output of such a unit as mentioned above, it is all right so long as its interval is less than 63.6μs, horizontal scanning period of CRT for display 1, and it is an enough time for CPU 5, etc. by the microcomputer using the MOS gate.
COPYRIGHT: (C)1980,JPO&Japio
JP10405878A 1978-08-25 1978-08-25 Video display device Granted JPS5530789A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10405878A JPS5530789A (en) 1978-08-25 1978-08-25 Video display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10405878A JPS5530789A (en) 1978-08-25 1978-08-25 Video display device

Publications (2)

Publication Number Publication Date
JPS5530789A true JPS5530789A (en) 1980-03-04
JPS6217767B2 JPS6217767B2 (en) 1987-04-20

Family

ID=14370580

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10405878A Granted JPS5530789A (en) 1978-08-25 1978-08-25 Video display device

Country Status (1)

Country Link
JP (1) JPS5530789A (en)

Also Published As

Publication number Publication date
JPS6217767B2 (en) 1987-04-20

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