JPH051948B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a measuring circuit for horizontal synchronizing pulses.

(Prior art) Conventionally, for example, in an IC circuit such as a CRT character generator that displays characters, etc. at an arbitrary position on a CRT, the vertical position on the CRT is determined by the number of horizontal synchronizing pulses after the vertical synchronizing pulse is generated. It was set by measuring.

Figure 3 shows one of the conventional examples, in which an arbitrary n number of T-flip-flops _TF1 ... _TF0 are connected in series and connected to the clock terminal T of the first-stage T-flip-flop _TF1 . A horizontal synchronizing pulse is input to the input terminal _I1 , and the reset terminals of each T-flip-flop are commonly connected to the inverter INV output. Further, a vertical synchronizing pulse is input to the input terminal _I2 connected to the input of the inverter INV.

Each T-flip-flop TF ₁ , TF ₂ , ...,
Non-inverting outputs Q ₁ , Q ₂ , ..., Q _o of TF ₃ are input terminals
As shown in the time chart shown in FIG. 4, the number of horizontal synchronization pulses after the fall of the vertical synchronization pulse is measured and expressed using the input signals I ₁ and I ₂ , that is, the horizontal synchronization pulse and the vertical synchronization pulse.

When the above-mentioned conventional example is used in a TV receiver and the electric field is weak, as shown in Figure 5a and b, when the horizontal synchronizing pulse is taken as a reference, the falling position of the vertical synchronizing pulse is before and after the horizontal synchronizing pulse. vibrate.

Now, for example, if we look at the positions of horizontal synchronization pulse measurement number 3 in Figure 5 a and b, they are points A and B, respectively, and points A and B are shifted by one horizontal synchronization pulse. , the horizontal synchronization pulse measurement circuit output deviates by one clock (1H) with respect to the slight vibration of the vertical synchronization pulse. In this development, the displayed characters on the CRT are displayed as oscillating at positions shifted by 1H, making it extremely difficult to see.

(Problems to be Solved by the Invention) As described above, the conventional horizontal synchronization pulse measuring circuit has the drawback that its output fluctuates by 1H in response to slight vibrations of the vertical synchronization pulse.

An object of the present invention is to provide a horizontal synchronization pulse measuring circuit that does not have output fluctuations due to slight vibrations of vertical synchronization pulses.

(Means for Solving the Problems) The horizontal synchronous pulse measurement circuit of the present invention includes a dummy pulse generation circuit, a reference signal generation circuit, an enable signal generation circuit, a V position detection & hold circuit, and a horizontal/dummy switching circuit. Ru.

The dummy pulse generation circuit decodes the horizontal position address counter output that divides the horizontal synchronization pulse rate by m, and generates a dummy pulse at l (0<l<m) address.

The reference signal generation circuit decodes the output of the horizontal position address counter and generates a reference signal that becomes active at h (0<h<l) or more.

The enable signal generation circuit decodes the horizontal position address counter output, and decodes the horizontal position address counter output from 0 to i (0<
hi<j) j~ including address and l address
An enable signal that becomes active at address k (i<jlk<m) is generated.

The V position detection and hold circuit detects the falling edge of the vertical sync pulse by latching the reference signal when the enable signal is active and holding the previous state when the enable signal is not active. It is detected whether the downlink timing is near the horizontal synchronizing pulse (addresses 0 to h).

The horizontal/dummy switching circuit switches the switch to the dummy pulse generation circuit only once after the fall of the vertical synchronization pulse when the vertical position detection circuit output is active, that is, the fall of the vertical synchronization pulse is near the horizontal synchronization pulse. and outputs a dummy pulse. In all other conditions, switch to the horizontal side,
Outputs horizontal sync pulse.

By using the output of the horizontal/dummy switching circuit as the input clock of this horizontal synchronizing pulse measuring circuit, a horizontal synchronizing pulse measuring circuit that does not have output fluctuations due to slight vibrations of the vertical synchronizing pulse can be obtained.

(Example) Hereinafter, the present invention will be described in more detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. The output of a 24-address counter circuit A1 that divides the horizontal synchronizing pulse rate into 24 includes three circuit blocks, namely, a dummy pulse that outputs a dummy pulse at the fifth address. Generation circuit A ₂ , Reference circuit A ₃ that outputs an “H” active signal at the fourth address or higher, Enable circuit that outputs an “L” active signal at the 0th address and the 5th address
A ₄ is connected, and the reference circuit output, enable circuit output, and vertical synchronization pulse are input to the vertical position detection and hold circuit A _5. When the enable signal is active, the reference signal is input at the falling timing of the vertical synchronization pulse. latches, and when the enable signal is inactive,
By maintaining the previous state, it is determined whether the vibration range of the falling position of the vertical sync pulse is within 3 addresses including the horizontal sync pulse, and the output, horizontal sync pulse, dummy pulse, vertical The synchronizing pulse is input to the horizontal/dummy switching circuit _A6 , and the horizontal/dummy switching circuit output _A6 is used as the clock for the measuring circuit _A7 .

Time charts of this embodiment are shown in FIGS. 2a and 2b, which correspond to FIGS. 5a and 5b, which are time charts of FIG. 3 showing the conventional circuit.

For example, when the vertical synchronizing pulse falls within the 0th address as shown in Figure 2a, that is, when the enable signal is "L" active and the reference signal is "L" non-active, the vertical synchronizing pulse falls. Yes, vertical position detection and hold circuit
A ₅ latches the reference signal "L" and transmits it to the horizontal/dummy switching circuit A ₆ , so that the horizontal/dummy switching circuit A ₆ outputs a dummy pulse and is simultaneously switched to horizontal output, so the vertical synchronizing pulse A dummy pulse is output only immediately after the falling edge of , and thereafter a horizontal synchronizing pulse is output.

Through these series of operations, the outputs Q ₁ , Q ₂ , ... Q _o of the horizontal synchronization pulse measurement circuit A ₇ (however, only outputs Q ₁ and Q ₂ are shown as representative in Figure 2)
Unlike Figure a, the count number is one clock higher, similar to Figure 5B. Also, as shown in Figure 2b, if there is a fall of the vertical synchronization pulse within the 23rd address, for example, the enable signal becomes "H" and non-active, so the vertical position detection & hold circuit generates a new reference signal. Since the previous state is maintained without latch and transmitted to the horizontal/dummy switching circuit, when a dummy pulse is output after the fall of the previous vertical synchronization pulse, it is output this time as well, and the time chart at this time is vertical synchronization. Except for the pulse falling position, it is exactly the same as Fig. 2a, and if the dummy pulse was not output immediately after the vertical synchronization pulse fell last time, it will not be output this time either, and the time chart at this time is shown in Fig. 5b. .

The falling positions of the output Q ₂ in Figure 2 a and b are exactly the same, and the subsequent change points are also the falling points of the horizontal synchronization pulse in Figure 2 a and b, so according to the present invention, vertical synchronization A horizontal synchronous pulse measuring circuit with no output fluctuation even when slight vibrations occur before and after the falling edge of the pulse can be obtained.

(Effects of the Invention) When the present invention is particularly applied to a CRT character generator, the horizontal synchronization pulse provides an easy-to-see screen without vertical vibration of the display character even under conditions where there is slight vibration of the vertical synchronization pulse such as a weak electric field. We can provide measurement circuits.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of an embodiment of the horizontal synchronization pulse measuring circuit of the present invention, Figures 2a and b are time charts showing the operation of an embodiment of the invention, and Figure 3 is a conventional horizontal synchronization pulse measurement circuit. The circuit diagrams of the pulse measuring circuit, FIG. 4 and FIGS. 5a and 5b, are time charts showing the operation of the conventional example. I ₁ , I ₁₁ ... Horizontal sync pulse input terminal, I ₂ , I ₁₂ ...
...Vertical synchronization pulse input terminal, TF _1~o , TF _11~1o ...
...Toggle flip-flop with reset terminal,
I _NV1 , I _NV11 ... Inverter, A ₁ ... Address counter circuit, A ₂ ... Dummy pulse generation circuit, A ₃ ...
…Reference signal, A ₄ …Enable circuit,
A ₅ ... Vertical position detection and hold circuit, A ₆ ...
...Horizontal/dummy switching circuit, A ₇ ...Measurement circuit.

Claims (1)

[Claims] 1. In the horizontal synchronization pulse measurement circuit that resets with a vertical synchronization pulse and measures the number of subsequent horizontal synchronization pulses, l (0 < l
<m) A dummy pulse generation circuit that generates a dummy pulse at an address, a reference signal generation circuit that generates a reference signal that becomes active at or above h (0<h<l) addresses from the decoded output of the horizontal address counter, and a horizontal address An enable signal generation circuit generates an enable signal that becomes active at 0 to i addresses including h and j to k addresses including l address from the decoded output of the counter, and the enable signal becomes active at the falling timing of the vertical synchronization pulse. a vertical position detection and hold circuit that latches the reference signal when , and holds the previous state when the enable signal is not active; and when the output of the vertical position detection and hold circuit is active, after the falling edge of the vertical synchronization pulse. a horizontal/dummy switching circuit that switches to the dummy pulse generation circuit side only once and switches to the horizontal synchronizing pulse side in all other states; and a measurement circuit that uses the output pulse of the horizontal/dummy switching circuit as a clock input. A horizontal synchronous pulse measurement circuit characterized by comprising: