JP2622189B2 - Liquid crystal display signal processing circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a circuit for processing a display signal supplied to a liquid crystal display device.

2. Description of the Related Art Conventionally, when displaying a halftone monotone on a liquid crystal display element for a long time, one kind of halftone level signal is supplied over the entire display region of the halftone.

[Problem to be Solved by the Invention] In such a conventional circuit, since one kind of halftone level signal is applied at a constant level for a long time,
There is a problem that a DC component is applied to the liquid crystal display element and the life of the liquid crystal display element is shortened.

Accordingly, an object of the present invention is to prevent a DC component from being applied even when a halftone monotone is displayed on a liquid crystal display element for a long time, thereby preventing the life from being shortened.

[Means for Solving the Problems] In order to solve the above problems, a liquid crystal display signal processing circuit of the present invention generates two types of halftone level signals in a display signal processing circuit supplied to a liquid crystal display element. A signal generation circuit, a switch circuit for alternately switching the two types of halftone level signals for each dot, and an AND circuit for performing a logical product of an output signal of the switch circuit and a display timing signal indicating a display area. The liquid crystal display device is provided with a halftone monotone display in a predetermined area.

[Operation] In the above-described configuration, two types of halftone level signals are obtained by the signal generation circuits 1 to 4, and the two types of halftone level signals are alternately switched for each dot by the switch circuit 5. The output signal of the circuit 5 is supplied to the liquid crystal display device as a halftone monotone signal.

Therefore, since two types of halftone levels are alternately displayed for each dot of the liquid crystal display element, if one dot of the liquid crystal display element is sufficiently fine, it is apparently an intermediate level between the two types of halftone levels. Will be seen as a monotone screen.

Since two types of halftone level signals are alternately supplied for each dot of the liquid crystal display element, no DC component is applied even when halftone monotone is displayed on the liquid crystal display element for a long time. It is possible to prevent the display element from deteriorating and shortening the life.

Embodiment An embodiment of the present invention will be described below with reference to FIG.

In the figure, 1 is a CPU including software,
2 is the data bus.

The CPU 1 sequentially supplies two types of halftone level signals S1 and S2 set by software to the latch circuits 3 and 4 via the data bus 2.

The latch pulse PLA1 is supplied from the CPU 1 to the latch circuit 3 at the timing when the halftone level signal S1 is supplied. As a result, the latch circuit 3 receives and holds the signal S1.

Further, the latch circuit 4 supplies the latch pulse PLA2 from the CPU 1 at the timing when the halftone level signal S2 is supplied.
Is supplied. As a result, the signal S2 is captured and held in the latch circuit 4.

Signals S1 and S2 output from latch circuits 3 and 4
Are supplied to the fixed terminals on the H and L sides of the switch circuit 5, respectively. The switching of the switch circuit 5 is controlled by a dot clock DCK supplied from a terminal 6, and is connected to the H side and the L side alternately for one dot period.
Therefore, the signals S1 and S2 are output from the switch circuit 5 alternately for one dot period (shown in FIG. 2A).

The output signal of the switch circuit 5 is supplied to an AND circuit 8. The display timing signal SDT is supplied to the AND circuit 8 from the terminal 7. This display timing signal is output from a liquid crystal display element control circuit (not shown), and is a signal which is at a high level "H" in correspondence with the area TMD for performing a halftone monotone display (FIG. 2B). Illustrated). Therefore, the signals S1 and S2 are output alternately for one dot period from the AND circuit 8 corresponding to the area TMD (illustrated in FIG. C).

Then, a signal output from the AND circuit 8 is led out to the terminal 9 as a halftone monotone signal SMT and supplied to a liquid crystal display element (not shown).

As described above, in this example, two types of halftone level signals S1 and S2 are supplied to the liquid crystal display element alternately for one dot period corresponding to the area TMD for displaying the halftone monotone. Therefore, if one dot of the liquid crystal display element is sufficiently fine, the viewer will see a monotone screen at an intermediate level between the two types of halftone levels.

According to this example, two types of halftone level signals S1 and S2
Is supplied to the liquid crystal display element alternately by one dot, so that a halftone monotone display is performed. Therefore, even when the halftone monotone is displayed on the liquid crystal display element for a long time, no DC component is applied, and the liquid crystal display element is not displayed. It is possible to prevent the life of the element from being shortened. Therefore, even if the halftone monotone display is performed for a long time, there is no problem.

In addition, this invention is, for example, NTSC-HD (high definition)
It is suitable for use in obtaining a halftone monotone signal to be inserted into a portion having no video signal in a video signal having a different display period as obtained by a converter.

[Effects of the Invention] As described above, according to the liquid crystal display signal processing circuit of the present invention, two types of halftone level signals are supplied alternately for each dot to a predetermined area of the liquid crystal display element. Since the monotone display is performed, even if the halftone monotone display is performed in a predetermined area of the liquid crystal display element for a long time, no DC component is applied, and the life of the liquid crystal display element can be prevented from being shortened.

That is, halftone monotone display can be performed for a long time without adverse effects such as shortening the life of the liquid crystal display element. For example, in the case of displaying video signals having different display periods, when halftone monotone display is performed in a region where there is no video signal, the life of the liquid crystal display element in the region where the halftone monotone display is performed is prevented from being shortened. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing waveforms of respective parts thereof. 1 CPU 2 Data bus 3 4 Latch circuit 5 Switch circuit 8 AND circuit

Claims (1)

(57) [Claims] 1. A circuit for processing a display signal supplied to a liquid crystal display element, comprising: a signal generating circuit for generating two types of halftone level signals; and alternately switching between the two types of halftone level signals for each dot. A liquid crystal display comprising: a switch circuit; and an AND circuit for performing a logical product of an output signal of the switch circuit and a display timing signal indicating a display area, and performing halftone monotone display in a predetermined area of the liquid crystal display element. Signal processing circuit.