JPH04204888A - Resetting circuit for data display device - Google Patents

Abstract

PURPOSE:To eliminate the defect that a previous screen remains at the time of mode changeover varying in the number of vertical lines by subjecting the reset pulse output from a reset pulse generating circuit to the resetting to a frame memory via a control circuit at the time of the changeover of the VGA (Video Graphic Array) mode. CONSTITUTION:The output of a detecting circuit 2 is obtd. according to the polarities of horizontal and vertical synchronizing signals when, for example, the vertical line in a state transition diagram changes over from 350, 400, 480 to the mode of other numbers, respectively. A reset pulse is added to the frame memory 5 and the memory of the previous screen is reset at the time of automatically changing the display mode. Then, a phase deviation is generated in the output vertical and horizontal changeover timing of switching transistors 17, 18, 19, 20 by adequately setting the time constants of integrating circuits 9, 10. Positive or negative pulses are respectively formed by an AND circuit 21 and an OR circuit 22 from such phase deviation. The remaining of the previous screen is eliminated in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Industrial Application Field The present invention relates to an information processing device using an LCD display element or the like, and particularly relates to an information processing device that uses an LCD display element, etc. The present invention relates to a reset pulse generation circuit for a data display device that prevents this.

(b) Conventional technology Generally, in information processing devices, VGA (Video
.

A display mode called Graphic Array (Graphic Array) mode is adopted, and for display switching in this VGA mode, the polarity signals of the horizontal synchronization signal and vertical synchronization signal are output from the information processing unit in accordance with the display mode. ing.

IC systems that can be used in this mode have been developed, and one of them is the 8-bit microcomputer HD66840LVIC manufactured by Hitachi. The basic system configuration is shown in Figure 1-1 on page 2 of the first edition published in November 1988 as an application note.

(8) Problems to be Solved by the Invention In the prior art described above, when switching the display mode in VGA mode using a frame memory and an LCD display element, the previous screen remains in the frame memory and is output to the next screen. (Lower P portion of FIG. 5) Therefore, the present invention proposes a new reset pulse generation circuit for a data display device that eliminates the above-mentioned inconvenience when switching in the VGA display mode.

(D) Means for Solving the Problems The present invention combines a detection circuit and a reset pulse generation circuit to which a horizontal synchronization signal and a vertical synchronization signal supplied from an information processing section are applied to a data display device, and The frame memory is configured to be reset by the output from the reset pulse generation circuit at the time of switching.

(*) Effect The present invention resets the frame memory by the reset pulse output from the reset pulse generation circuit via the control circuit when switching the VGA display mode, so that the previous screen does not change when switching to a mode with a different number of vertical lines. Any remaining defects are removed.

(f) Example The present invention will be explained according to the drawings. Fig. 1 is a circuit diagram showing the main parts of the circuit of the invention, Fig. 2 is a block diagram showing the system configuration, Fig. 3 is a waveform diagram showing a timing chart, FIG. 4 shows a state transition diagram, and FIG. 5 shows an explanatory state diagram of the screen.

In the drawings, (1) is an information processing unit, (2) is a detection circuit, (3) is a reset pulse generation circuit, (4) is a control circuit, (5) is a frame memory, and (6) is an LCD as a display device. Display element, (7) and (8) are synchronization terminals to which vertical and horizontal synchronization signals are applied, respectively, (9) and (10) are resistors (11
) (12) (13) (14) and capacitors (15) (
16), (17) (18) (19) (
20) is a switching transistor that is turned on and off by the synchronization signal, <21) is an AND gate, (22)
(23) is a monomulti circuit, (24) is an output terminal, and (25) is a clear (CLEAR) signal application terminal.

Next, the operation of the circuit of the present invention will be explained. In FIGS. 1 and 2, terminals (7) and (8) receive a vertical synchronizing signal (V, 5YNC) and a horizontal synchronizing signal (H, 5YNC), respectively. At this time, in IBM's VGA display mode, Table 1
As shown in the figure, the polarity of the synchronizing signal is determined corresponding to the number of vertical lines. These are the integrating circuit (9) (
10), a detection output is obtained by the detection circuit (2).

Mono multi circuit (
23).

Table 1 Table 2 For example, when the display mode is switched from vertical line 350 to vertical line 400, v, 5yNC are
In (a), the polarity of H-5YNC is reversed as shown in FIG. 3 (b), and a positive pulse shown in FIG. 3 (c) is output from the AND gate (21).

In Table 2, the monomulti circuit M (23) is configured to obtain outputs for the two states indicated by broken lines, so for example, CLEAR is high (H) as an input, vertical synchronization signal (A/'■ ) is low (L), horizontal synchronization signal (B/@
) rises to high (↑), the output Q becomes a positive pulse and Q becomes a negative pulse.

On the other hand, CLEAR is high (H), vertical synchronization signal (A/■)
falls from high (↓), horizontal synchronization signal (B/[F])
becomes high (H) level, output Q is a positive pulse, G
becomes a negative pulse, and the output appears as the case of ■ or ■.

In the state transition diagram in Figure 4, each vertical line is 350.40.
0,480 to other number modes, the detection circuit (2
) is obtained, and as a result, a reset pulse is automatically applied to the frame memory (5) when the display mode changes, and the memory of the previous screen is reset, so it does not remain on the screen as in the past. The regular screen shown in FIG. 6 appears.

Note that the vertical line 350. :! For switching of 400, AND and OR circuits (21) (2
Even if the polarity change after passing through 2) is applied to the truth table of monomulti (23), no output pulse is generated, but the integrator circuit (
9) By appropriately setting the time constant of (10), switching transistors (17), (18) and (19) (
A phase shift occurs in the output vertical and horizontal switching timings of 20), and this phase shift allows the AND circuit (21) and OR circuit (22) to generate positive or negative pulses, respectively.

The above Figure 4 (a), (b), and (c) are examples of ■ in Table 2,
Figures (D), (*), and (F) show examples of ■ in Table 2.

By changing the polarity of H, SYNC, V, and 5YNC through an AND circuit and an OR circuit, a reset pulse necessary for switching each mode of the vertical line 350G-4400→480 is obtained, and the previous screen is Frame rest can be prevented.

(G) Effects of the Invention According to the pulse generation circuit of the data display device of the present invention, V
When the number of vertical lines is reduced from 400 to 350 in the GA display mode, the data in the frame memory can be refreshed, whereas the previous screen remained in the frame memory. will be removed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a reset pulse generation circuit of a data display device of the present invention, and FIG. 2 is a block diagram of the main parts of the device.
FIG. 3 is an explanatory waveform diagram of the same device, FIG. 4 is an explanatory state transition diagram of the same device, FIG. 5 is a screen state diagram of a conventional data display device, and FIG. 6 is a screen of the same device of the present invention. A state diagram is shown. (1)...information processing section, (2)...detection circuit,
(3>...Reset pulse generation circuit, (4)...
Control circuit, (5)...Frame memory, (6)...
LCD display element, (7) (8)...Synchronization terminal, (2
3)...Mono multi circuit. Figure 1 Prefecture Figure 3 Figure 5 P Figure 6

Claims (1)

[Claims] (1) In a data display device equipped with an information processing section, a horizontal synchronization terminal, a vertical synchronization terminal, a frame memory, a control circuit, and a display element, a time constant circuit is connected to the power supply terminal, and the output side of the time constant circuit is connected to the power supply terminal. A reset pulse generation circuit is connected, the polarity of the horizontal and vertical synchronization signals corresponding to the VGA display mode is detected by the polarity detection circuit, the reset pulse generation circuit is driven to output a reset pulse, and the reset pulse is used to control the control circuit. A reset circuit for a data display device, characterized in that it operates and resets a frame memory.