JP3267712B2 - Display device and display method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device and a display control method, and more particularly to a display device using a TFT (thin film transistor) liquid crystal display panel and a technique effective for use in the display control method.

[0002]

2. Description of the Related Art In a display device using a conventional TFT liquid crystal display panel, it is mainly used for personal computers.
The display size is such as 40 pixels × 480 lines or 680 pixels × 400 lines. Further, depending on the display specifications (for example, VGA) of the personal computer, the start position and the end position of the display are determined. in this case,
The display control device receives the vertical synchronizing signal and the horizontal synchronizing signal from the main computer, and controls the display of the TFT liquid crystal display device.

[0003]

In a display device using a conventional TFT display panel, it is necessary to incorporate a control circuit and the like in accordance with the specifications of a personal computer on which the display device is mounted. Therefore, it lacks versatility and is not suitable for mass production.

An object of the present invention is to provide a display device and a display control method which are easy to control and have high versatility. The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[0005]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, by using the horizontal synchronization signal and the display data valid signal, the display data input during the period in which the display data valid signal is set is valid and fetched serially, and at the timing when the display data valid signal is reset, The display data fetched serially is transferred in parallel and output as a pixel signal for one scanning line of the display panel, and the absence of a display data valid signal between a plurality of horizontal synchronization signals is defined as a vertical blanking period. .

[0006]

According to the above-mentioned means, if it is less than the maximum display for one scanning line of the display panel in the horizontal direction, it corresponds to the display data valid period and has an arbitrary size range, and the vertical direction is less than the maximum display line Then, the display operation can be performed in an arbitrary range defined by two consecutive horizontal synchronization signals.

[0007]

FIG. 1 is a timing chart for explaining a display control method according to the present invention. In the figure,
An example using a TFT liquid crystal display panel is shown. There are two basic control signals, a horizontal synchronization signal and a display data valid signal. In addition, it goes without saying that display data necessary for the display operation and a clock pulse for serially transferring the display data are also required.

After the horizontal synchronizing signal, a display data valid signal is formed corresponding to the display range. The period in which the display data valid signal is set defines the horizontal range of the display screen. That is, the display data valid signal corresponds to the number of clock pulses for transferring the display data corresponding to the display range. For example, the number of pixels of one line of the display panel to be used is 1024, and the display data of 1024 pixels is transferred when the entire display is performed.
It corresponds to four clock pulses. 1 as above
When only 640 pixels are displayed on 024 display screens, the period in which the display data valid signal is set corresponds to the number of clock pulses for serially transferring data of 640 pixels. Such a horizontal synchronizing signal and a display data valid signal are formed by a main body computer. Also, display data to be displayed and a clock pulse for transferring the display data are supplied at the same time.

The vertical direction of one screen is defined by two consecutive horizontal synchronizing signals. That is, in the display range, 2
Although the display data valid signal is always inserted between two horizontal synchronizing signals, the display data valid signal is not output during the vertical blanking period. In the figure, a horizontal period for two cycles is defined as a vertical retrace period by three horizontal synchronization signals after the display data of the last line is input, and the horizontal synchronization signal input thereafter is defined. Judge as the first line,
Start serial capture of display data corresponding to the display data valid signal.

FIG. 2 is a block diagram showing one embodiment of the display device according to the present invention. The display control device includes:
The horizontal synchronizing signal, the display data valid signal, the display data, and the clock for serial input thereof are supplied as described above. The display control device forms a clock pulse CL2 for serial input, a clock pulse CL1 for parallel transfer, a clock pulse CL3 for scanning operation of the gate driver, and an operation start FLM from these signals.

The liquid crystal display panel TFT-LCD is composed of a large panel. Odd-numbered and even-numbered signal lines of the liquid crystal panel are divided up and down, and a drain driver composed of a semiconductor integrated circuit is provided on the upper and lower sides.

When the first stage drain driver finishes taking in data by the serial input clock pulse CL2, it immediately enters the low power consumption mode. Then, the output signal is set to the low level, and the drain driver of the next stage starts the operation, respectively, and captures data by the subsequent clock pulse. Hereinafter, similarly, input data is taken in up to the final stage drain driver. However, in this embodiment, since the display screen is defined by the set period of the display data valid signal,
Data is not always taken up to the drain driver at the last stage. Upon completion of the data capture, a clock pulse CL1 is generated to transfer the captured latch data to a line data latch circuit, and start capturing serial data corresponding to the next line.

The scanning line electrodes are driven by a gate driver. This gate driver is also provided in a plurality of semiconductor integrated circuits corresponding to the number of scanning line electrodes, and the first gate driver is supplied with the FLM signal. Thus, the selection signal for the first line is set. Thereafter, in synchronization with the clock pulse CL3, the scanning line electrodes are sequentially selected, the TFTs connected thereto are turned on, and the pixel signals output in parallel from the drain driver are held in the pixel electrodes.

FIG. 3 is a block diagram showing one embodiment of the display control device. This display control device is shown in FIG.
This will be described with reference to the timing chart of FIG. The CL2 generation circuit uses the display data valid signal as an enable signal, and when it is set to a high active level, outputs a clock input together with the display data as a clock pulse CL2 for serial capture of the drain driver.

The display data valid signal is supplied to a fall detecting circuit, which detects the timing at which the display data valid signal is reset from a high active level to a low level and activates the CL1 generating circuit. The CL1 generation circuit generates a clock pulse CL1 in synchronization with the timing signal.

The display data valid signal is supplied to a rise detection circuit. The CL3 generation circuit receives the rising detection signal and the output signal of the flip-flop FF2 that performs vertical blanking detection described below, and generates a clock pulse CL3 based on the rising edge detection signal during a period other than the vertical blanking period. Generate This clock pulse CL3
Thereby, the scanning line selection signal is switched by the gate driver.

The flip-flops FF1 and FF2 detect a vertical blanking period. Flip-flop FF1
Is a reset-priority JK flip-flop circuit provided by an inverter circuit and a logic gate circuit provided at its input, to which a display data valid signal is supplied. The output signal of the flip-flop FF1 is supplied to the D flip-flop FF2. The horizontal synchronization signal is supplied to the clock terminal D-CK of the flip-flop FF2.

In the vertical blanking period detection circuit, as shown in the timing chart of FIG. 5, when a horizontal synchronizing signal is generated in a normal display period, a display data valid signal is subsequently input. As a result, the JK flip-flop is always reset. However, in the vertical retrace period, 1
Even if the second horizontal synchronizing signal is input, the display data valid signal is not input.
The flip-flop is set. With this set output,
The D-type flip-flop FF2 is also set by the horizontal synchronization signal. The FLM generation circuit uses the flip-flop F
An FLM signal is generated by the output signal of F2 and the clock pulse CL3.

Then, the display data of the first line is captured by the horizontal synchronizing signal and the display data valid signal, and the FLM signal is reset by the clock pulse CL3. As a result, the gate driver forms a selection signal for the first line, and the display data is written in parallel to the captured first line pixels in synchronization with the clock pulse CL1 (not shown). The flip-flop FF1 is reset by the display data valid signal, and the flip-flop FF2 is reset by the next horizontal synchronization signal.

In this embodiment, a timing signal necessary for a display operation of a TFT liquid crystal display panel is formed by using a horizontal synchronizing signal, a display data valid signal and its serial transfer clock pulse. Therefore, a display screen of an arbitrary size can be set within the display range of the TFT liquid crystal display panel. That is, the horizontal size of the screen is determined by the number of clock pulses during the period in which the display data valid signal is set. The size of the screen in the vertical direction is determined by a vertical blanking period defined by a combination of a horizontal synchronization signal and a display data valid signal.

The left end of the horizontal display screen can be set by inputting the display data valid signal and dummy display data for instructing black display. That is, it is possible to obtain a display screen in a range obtained by subtracting the number of dummy display data corresponding to black display from the number of clock pulses in the display data valid signal and the period.

In the display device and the display control direction as in this embodiment, the configuration of the display screen is determined by software by a host system such as a microcomputer. Thus, the mass productivity can be higher than the versatility of the display device. In the display device, a circuit for processing (recognizing) the display size can be omitted.

The operation and effect obtained from the above embodiment are as follows. That is, (1) Using the horizontal synchronization signal and the display data valid signal,
Display data input during the period in which the display data valid signal is set is valid and fetched serially.When the display data valid signal is reset, the serially fetched display data is transferred in parallel and displayed. A pixel is output as a pixel signal for one scanning line of the panel, and the absence of a display data valid signal between a plurality of horizontal synchronizing signals is defined as a vertical blanking period. If the display operation is less than the maximum display line, the display operation is performed in an arbitrary size range corresponding to the display data valid period. The effect is obtained.

(2) According to the above (1), it is possible to obtain a display device having high versatility, and it is possible to obtain the effect of increasing mass productivity.

(3) According to the above (1), an effect that a circuit for processing a display size can be eliminated can be obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, FIG.
, A register for designating the left end of the display screen and a counter circuit may be provided. That is, during the period when the counter is operating, dummy display data may be internally generated and captured, and after the display data valid signal is set, the display data may be serially captured subsequently. . The circuit for detecting the vertical blanking period and the specific circuit for performing the first line processing (first line marker) may be any circuit as long as it can identify a combination of signals as described above. The present invention can be widely used as a display device and a display control method.

[0027]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, by using the horizontal synchronization signal and the display data valid signal, the display data input during the period in which the display data valid signal is set is valid and fetched serially, and at the timing when the display data valid signal is reset, The display data fetched serially is transferred in parallel and output as a pixel signal for one scanning line of the display panel, and the absence of a display data valid signal between a plurality of horizontal synchronization signals is defined as a vertical blanking period. Therefore, in the horizontal direction, if it is less than the maximum display for one scanning line of the display panel, it corresponds to the display data valid period within an arbitrary size range. The display operation can be performed in any range defined by the synchronization signal.

[Brief description of the drawings]

FIG. 1 is a basic timing chart of one embodiment for explaining a display control method according to the present invention.

FIG. 2 is a block diagram showing one embodiment of a display device according to the present invention.

FIG. 3 is a block diagram showing one embodiment of the display control device of FIG. 2;

FIG. 4 is a timing chart showing an example of the operation of the display control device of FIG.

FIG. 5 is a timing chart for explaining a detection operation of a vertical blanking period of the display control device of FIG. 3;

[Explanation of symbols]

TFT-LCD: TFT liquid crystal display panel, FF1: JK
Flip-flop, FF2 ... D-type flip-flop.

Claims (4)

(57) [Claims] And 1. A horizontal synchronizing signal, and display data, and a display panel for a display control apparatus and Viewing the data valid signal is inputted, the display of the display data for a plurality of lines in one frame period, the display A driver controlled by a control device to drive the display panel, the display device comprising: a horizontal synchronization signal input to the display control device;
The display data valid signal is provided between the horizontal signal signals.
That the data valid signal is not valid multiple times
A vertical blanking period is set by combination, and the display control device sets the display data between horizontal synchronization signals.
If the valid signal indicates valid, the signal before the horizontal sync signal
Before the display data valid signal was input during the period indicating validity
The display data as one line of display data.
Input to the latch circuit of
The displayed data for one line is stored on the display panel.
The display data valid signal of only one line indicates valid.
Display in the area corresponding to the length of the
The display data for a plurality of lines to the display panel.
The driver so that the display is performed in order from the first line.
Controls, the display data valid signal among the horizontal synchronizing signal have a detection circuit for detecting that not valid and the detection circuit
First, after the detection, the display data valid signal
The display data entered in the period shown
A display device, which is a device that controls the driver so as to display a next frame period as display data of a first line . 2. The display device according to claim 1, wherein the display panel is a liquid crystal display panel. 3. A display apparatus comprising: a horizontal synchronizing signal; display data;
Data valid signal is input to the screen during one frame period.
A display method for displaying several lines, wherein the input horizontal synchronizing signal and the display data valid signal are input.
The display data valid signal is valid between horizontal signal signals.
More perpendicular to the combination of continuous several times that not a
Set a blanking period, and the display data valid signal indicates valid between horizontal sync signals
If the display data valid signal between the horizontal synchronizing signals
The display data input during the period when
The display data of the driver to the latch circuit of the driver.
For one line captured by the latch circuit.
Display data before any one line of the display panel
Area corresponding to the length that the display data valid signal indicates valid
And before a plurality of lines in one frame period.
The display data is sequentially displayed on the display panel from the first line.
When the display is performed and the display data valid signal is valid between the horizontal synchronizing signals,
If it is detected that there is no
Display data input during the period when the display data valid signal indicates valid
Data with the display data of the first line in the next frame period.
And displaying the next frame period . 4. The display method according to claim 3 , wherein the display is performed on a screen of a liquid crystal display device.