JPH08166776A - Display device - Google Patents

Abstract

PURPOSE: To make display data easy to look by moving a display image and performing data processing when the number of display pixels of a display section is not the same as the number of display pixels of transmitted display data. CONSTITUTION: A value of a register 22 is defined as (a), the number of all display lines on a liquid crystal display panel stored in a vertical section 11 of a display fixed constant section 10 is defined as (b), and a value of a register 32 is defined as (c). A value of (a) is compared with a value of (b) in a comparison section 40, and if the compared result is a=b, received display data is outputted to a drain driver as it is. Also, a value of (a) is compared with a value of (b) in a comparison section 40, if the compared result is a<b, calculation of c-((b-a)/2) is performed in an operation section 50, the value of the operation result of this operation section 50 is compared with a counter value of a counter 31 of a first display line recognizing section 30, and when they are equal, a frame start instruction signal is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display device for displaying display data when the number of display pixels of the display data does not match the number of display pixels of the display unit of the display device. The present invention relates to a technique effectively applied to a display control device that moves the center of a part.

[0002]

2. Description of the Related Art A conventional TFT (Thin Film Transistor) is used for a conventional display device.
A liquid crystal display device will be described as an example.

FIG. 7 is a block diagram showing a schematic structure of a conventional TFT liquid crystal display device.

In FIG. 7, a liquid crystal display panel (LCD)
Is composed of 640 × 3 × 480 pixels, the drain drivers 110 are arranged above and below a liquid crystal display panel (LCD), and the upper and lower drain drivers 110 are alternately connected to the drain lines of thin film transistors (TFT). Supplying a voltage for driving a liquid crystal to a thin film transistor (TFT).

A gate driver 120 arranged on the side surface of a liquid crystal display panel (LCD) is connected to the gate line of the thin film transistor (TFT) to supply a voltage to the gate of the thin film transistor (TFT) for one horizontal operation time.

A display control device 100 composed of one semiconductor integrated circuit (LSI) receives display data and a display control signal from a main body computer, and based on this, outputs a display control signal to a drain driver 110 and a gate driver 120. It is generated and drives the drain driver 110 and the gate driver 120.

In this case, the display data from the main body computer is transferred in unit of one pixel, that is, each of the data of red (R), green (G) and blue (B) is grouped and transferred every unit time. .

Here, the display data is composed of 12 bits of 4 bits for each color.

Further, since the drain driver 110 is arranged above and below, the output for driving the drain driver 110 from the display control device 100 has two systems for both the display control signal and the display data bus.

Display control signals sent from the main body computer to the display control device 100 include a vertical synchronizing signal, a horizontal synchronizing signal, a display timing signal and a clock.

FIG. 8 is a diagram showing a timing chart of the display control signal from the main body computer shown in FIG. 1 and the display control signal generated by the display control device.

When the display timing signal (DTMG) is input, the display control device 100 determines that this is the display start position, and outputs the received display data to the drain driver 110.

At this time, a clock (D2) is also output as a latch clock for the drain driver 110.

The clock (D2) is the drain driver 1
Due to the arrangement of 10 in the vertical direction, the clock input from the main body computer is divided by two, and the drain driver 110 stores the display data in order.

Display Timing Signal (DTMG)
Is completed or when a predetermined fixed time has passed since the display timing signal (DTMG) was inputted, it is assumed that the display data for one horizontal is completed,
A clock (D1) which is a display control signal for outputting the display data stored in the drain driver 110 to the drain line of the thin film transistor (TFT) is output to the drain driver 110.

It should be noted that after the vertical synchronizing signal (VSYNC) is input, the first display timing signal (DTM)
G) is input, it is determined to be the first display line and a frame start instruction signal (HSG) is output to the gate driver 120.

The clock (G) serves as a shift clock to the gate driver 120.

The TFT liquid crystal display device shown in FIG. 7 is a VGA (Video Graphics A) which is one of the display architectures of a personal computer.
It is a TFT liquid crystal display device conforming to the rray).

The VGA has several display modes, and examples thereof include a 350 line display mode, a 400 line display mode, and a 480 line display mode.

A method for distinguishing these modes in a TFT liquid crystal display device is to use a vertical sync signal (VSYN).
C) and the polarity of the horizontal synchronizing signal (HSYNC) are combined.

Table 1 shows these combinations and display line modes.

[0022]

[Table 1]

If display is performed without recognizing this mode, the display data will stick to the upper side of the display unit in the 350 line mode (or 400 line mode), and 130 lines (or below) will be displayed. (80 lines) is a black display or a double copy of the display, resulting in a display that is very difficult to see.

In order to solve this, the display control device 10
The line mode is determined at 0, and in the case of 350 line mode (or 400 line mode), if the frame start instruction signal (FSG) is generated 65 lines (or 40 lines) before the display data is input, The display data moves to the center of the display unit.

This processing is called centering, which makes the display easy to see.

[0026]

As described in the above-mentioned prior art, in the case of a system in which the number of display pixels of the display unit of the display device is 640 horizontal by 480 vertical and the target is a limited system such as VGA, Mode determination and display centering can be easily handled.

However, if this is not VGA and the number of display pixels of the display unit of the display device is higher, only a maximum of four modes can be used in the combination of synchronization signals. Further, considering the versatility, there is a problem in that setting the mode naturally imposes a use restriction.

The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a display device with the number of display pixels of a display unit,
It is an object of the present invention to provide a technique that makes it possible to see the display data displayed on the display unit when the number of display pixels of the display data does not match.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0030]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

(1) A display device comprising a display section, a display control circuit for driving the display section based on display data from the main body section, and a display control signal including at least a display timing signal. A circuit compares a pulse count unit that counts the number of pulses of the display timing signal from the main body unit within one frame period with the number of pulses counted by the pulse count unit and the total number of display lines of the display unit. Section and the number of pulses counted by the pulse counting section based on the comparison result of the comparing section is less than the total number of display lines of the display section, the display data from the main body section is moved in a direction perpendicular to the display line. To display the display data in the center of the display unit. Characterized by including and.

(2) In the above-mentioned means (1), the display control circuit further comprises a display data copying circuit for increasing the display data by copying the display data from the main body at least once. Is characterized by.

(3) A display device comprising a display section, a display control circuit for driving the display section based on display data from the main body section, and a display control signal including at least a display timing signal. A circuit compares a pulse count unit that counts the number of pulses of the display timing signal from the main body unit within one frame period with the number of pulses counted by the pulse count unit and the total number of display lines of the display unit. Section and the number of pulses counted by the pulse counting section based on the comparison result of the comparing section is larger than the total number of display lines of the display section, the display data from the main body is thinned out every predetermined display line. And a thinning circuit for displaying.

(4) A display device comprising a display section, a display control circuit for driving the display section based on display data from the main body section and a display control signal including at least a clock signal and a display timing signal. The display control circuit counts the number of pulses of the clock signal from the main body within the valid period of the display timing signal from the main body, a pulse count unit, and the number of pulses counted by the pulse count unit and the display unit. A comparing unit that compares the total number of pixels per display line, and if the number of pulses counted by the pulse counting unit based on the comparison result of the comparing unit is less than the total number of pixels per display line of the display unit. , Display data from the main unit can be displayed by moving it in a direction horizontal to the display line. Characterized by comprising a centering circuit for displaying data in the center of the display unit.

(5) A display device comprising a display section, a display control circuit for driving the display section based on display data from the main body section and a display control signal including at least a clock signal and a display timing signal. The display control circuit counts the number of pulses of the clock signal from the main body within the valid period of the display timing signal from the main body, a pulse count unit, and the number of pulses counted by the pulse count unit and the display unit. A comparing unit that compares the total number of pixels per display line, and if the number of pulses counted by the pulse counting unit based on the comparison result of the comparing unit is greater than the total number of pixels per display line of the display unit. ,
And a thinning circuit for thinning the display data per line of the display data from the main body for each predetermined pixel to display the display data.

[0036]

The display timing signal sent from the main body is a signal indicating the effective range of the display data within one frame time, and the length and the number thereof are determined according to the display data from the main body. To be done.

According to each of the above means, the display device determines how many display timing signals are input in one horizontal time, and how many times (pulse number) is input in one frame time. Thus, the display control device grasps the number of display pixels of display data from the main body side.

Then, this is compared with the number of display pixels of the display unit of the display device, and when the number of display pixels of the display data is small, the display data is centered, and conversely, the number of display pixels of the display data is large. For example, by thinning the display data to reduce the number of display pixels in the display unit and displaying the display data, it is possible to make the display data displayed on the display unit easier to see.

Further, there is no malfunction even if display data processing is performed based on the display timing signal.
Furthermore, since the display timing signal is already on the interface, it is not necessary to adopt a new interface.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a liquid crystal display device will be described below with reference to the drawings.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

The schematic structure of the liquid crystal display device to which the present invention is applied is the same as that of the conventional liquid crystal display device shown in FIG.

The liquid crystal display device to which the present invention is applied has a centering circuit and a thinning circuit for centering in the display control device 100.

[Embodiment 1] FIG. 1 is a block diagram showing a circuit configuration of a centering circuit and a thinning circuit in a display control device of a liquid crystal display device which is an embodiment (embodiment 1) of the present invention.

The centering circuit and the decimation circuit of the first embodiment are circuits for performing the centering process and the decimation process in the vertical direction.

In FIG. 1, reference numeral 10 is a display fixed constant part (RO) composed of a ROM (Read Only Memory).
M), 20 is a display timing signal pulse counting unit, 30 is a first display line recognition unit, 40, 70, 80
Is a comparison unit, 50 and 60 are arithmetic units, and 90 is a thinning-out line counter.

The display fixed constant part 3 is the vertical part 11
The vertical portion 11 includes the number of pixels in the vertical direction of the liquid crystal display panel (LCD) (the number of display lines).
However, the horizontal section 12 stores the number of pixels in the horizontal direction.

The display timing signal pulse counting section 20 has a counter 21 and a register 22. In the counter 21, after the vertical synchronizing signal (VSYNC) is input,
That is, after the vertical period period, the next vertical synchronization signal (VSY
Display timing signal (DTMG) is set to 1 until the display timing signal (DTMG) is not input during one line, that is, until the start of the vertical period, until NC) is input. Count DTMG).

Further, the counter value at that time is stored in the register 2
Hold at 2.

The first display line recognition section 30 recognizes the first display line for displaying the display data after the vertical synchronizing signal (VSYNC) is input, and has a counter 21 and a register 22.

Counter 21 of first display line recognition unit 30
Then, after the vertical synchronizing signal (VSYNC) is input, the horizontal synchronizing signal (HSYNC) is counted with the input of the horizontal synchronizing signal (HSYNC) as 1 until the first display timing signal (DTMG) is input.

The counter value at that time, that is, the first
The th display line is held in register 32.

That is, the first display line recognition unit 30 determines that the first display timing signal (DTMG) input after the vertical synchronization signal (VSYNC) is input is the first display line for displaying the display data.

The thinning-out line counter 90 is for removing display data of a predetermined line from the display data of all lines input from the main computer, and the counter 91 of the thinning-out line counter 90 is a vertical synchronizing signal ( After the input of VSYNC), the display timing signal (DTMG) is set to 1 and the display timing signal is counted.

Further, the counter 91 is cleared by the coincidence signal of the comparing section 80.

FIG. 2 is a diagram showing a time chart of the display control signal from the main body computer shown in FIG. 1 and the display control signal generated by the display control device 100. FIG.
It is a time chart when all the display lines of a liquid crystal display panel (LCD) are 16 lines and only the display data for 8 lines was input into it.

The register 22 of the display timing signal pulse counting section 2 stores the total number of lines of display data.

Next, the centering process in the vertical direction will be described with reference to FIGS.

Here, the value of the register 22 is set to a (see FIG. 2).
Then, a = 8), display fixed constant part (ROM) 1
Liquid crystal display panel (LC
It is assumed that the total number of display lines of D) is b (b = 16 in FIG. 2) and the value of the register 32 is c (c = 7 in FIG. 2).

In the comparison unit 40, the values of a and b are compared, and if the comparison result is a = b, naturally, no data processing or the like is performed, and the received display data is output to the drain driver 110 as it is.

The frame start instruction signal (FSG) is the first
When the display data of the th display line is received, it is output to the gate driver 120.

Further, the comparing section 40 compares the values of a and b, and when the comparison result is a <b, the calculating section 50 calculates c-((b-a) / 2). And then
The calculation result of the calculation unit 50 and the first display line recognition unit 30
The counter value of the counter 31 is compared in the comparison unit 70, and if they match, the frame start instruction signal (FSG)
Is output.

That is, as shown in FIG. 2, (b-a) / 2 lines before the first display line (c), that is, c-
The frame start instruction signal (FSG) is output from the ((ba) / 2) th line (third line in FIG. 2).

From here, until the display data of the first display line is input, the black display data is output to the drain driver 110 so that the liquid crystal display panel (LCD) displays black.

In order to display black on the liquid crystal display panel (LCD), when the display timing signal (DTMG) is valid by taking the logical product of the display data from the main body computer and the display timing signal (DTMG). The display data can be validated in the above step, and the display data can be invalidated in other cases.

The display data transmitted from the main body computer is output to the drain driver 110 from the first display line to the display line a.

Further, black display data is also applied to the drain driver 11 on the display line after the a display line.
Output to 0 and display black on the liquid crystal display panel (LCD).

FIG. 3 is a diagram showing a display result of the liquid crystal display panel (LCD) when centering is performed, in comparison with a case where centering is not performed.

As is clear from FIG. 3, when the above-mentioned centering is executed, the display data moves to the central portion of the liquid crystal display panel (LCD), so that the display screen can be easily seen.

Next, the vertical thinning process will be described.

In the comparison unit 40, the values of a and b are compared. If the comparison result is a> b, the operation unit 60 performs the operation of a / (ab), and this operation unit 60
And the counter 91 of the thinning line counter section
Is compared with the counter value in the comparison unit 80, and if they match, the shift clock (G) to the gate driver 120
Stop the pulse once.

That is, for every a / (ab) line interval,
The display data for the ab line is removed and output to the drain driver 110.

As a result, the display data becomes the b line, and all the display data is displayed on the liquid crystal display panel (LCD).

In this case, the frame start instruction signal (FS
G) outputs the display data of the first display line to the gate driver 120 when the display data is received.

[Embodiment 2] In Embodiment 1, when the difference of a <b is extremely large, for example, 2a <b, the same data is displayed on two lines and centered. There is.

FIG. 4 shows another embodiment (second embodiment) of the present invention.
FIG. 3 is a block diagram showing a circuit configuration of a centering circuit in the display control device of the liquid crystal display device.

The centering circuit of the second embodiment is a circuit that displays the same data on two lines and performs centering processing in the vertical direction.

In FIG. 4, the display fixed constant unit (ROM) 10, the display timing signal pulse counting unit 20, and the first display line recognition unit 3 shown in FIG.
0, the comparison unit 80, the calculation unit 60, and the thinning-out line counter 90 are omitted.

In FIG. 4, reference numeral 41 denotes a left shift circuit, and 41
Is a selector and 71 is an OR circuit.

The comparison section 40 compares the values of a and b, and if the comparison result is 2a <b, the left shift circuit 41 shifts the value of a to the left by 1 bit and doubles it. The doubled value of a is selected by the selector 42 and input to the calculation unit 50.

The comparison section 40 compares the values of a and b. If the comparison result is a <b, the selector 42 selects the value of a and inputs it to the arithmetic section 50.

When the comparison result is 2a <b, it is necessary to operate the gate shift clock (G) to the gate driver 120 at a half cycle as compared with the case where the comparison result is a <b. Therefore, as shown in FIG. 4, when the comparison result is 2a <b, the speed doubling process of the gate shift clock (G) to the gate driver 120 is performed.

As a result, the same display data can be displayed on two lines and centered on the liquid crystal display panel (LCD).

[Embodiment 3] FIG. 5 is a block diagram showing a circuit configuration of a centering circuit and a thinning circuit in a display control device of a liquid crystal display device according to another embodiment (Embodiment 3) of the present invention.

The centering circuit and the decimation circuit of the second embodiment are circuits for performing the centering process and the decimation process in the horizontal direction.

In FIG. 5, reference numeral 25 is a display timing signal clock length detector, 35 is a first display pixel recognizer, and 95 is a thinning counter.

The display timing signal clock length detecting section 25 has a counter 26 and a register 27. The counter 26 receives from the input of the display timing signal (DTMG) after the input of the horizontal synchronizing signal (HSYNC) to the end of the signal. Up to, the clock (CK) is counted with the input of the clock (CK) from the main body computer as 1.

Further, the counter value at that time is stored in the register 2
Hold at 7.

The first display pixel recognizing section 35 is for recognizing the first pixel of the display data on one display line after inputting the horizontal synchronizing signal (HSYNC), and has a counter 26 and a register 27. .

In the counter 26 of the first display pixel recognizing unit 35, the clock (CK) is set to 1 until the first display timing signal (DTMG) is input after the horizontal synchronizing signal (HSYNC) is input. C
K) is counted.

The counter value at that time is stored in the register 3
Hold at 7.

The thinning-out line counter 95 is for removing display data of a predetermined number of pixels from the display data per line input from the main body computer, and the counter 96 of the thinning-out line counter 95 is a horizontal synchronizing signal. After inputting (HSYNC), clock (C
The clock (CK) is counted with the input of K) as 1.

Further, the counter 96 is cleared by the coincidence signal of the comparing section 80.

FIG. 6 is a diagram showing a time chart of the display control signal from the main computer shown in FIG. 5 and the display control signal generated by the display control device. FIG. 6 shows one line of the liquid crystal display panel (LCD). 6 is a time chart when only display data having a smaller number of pixels than the number of pixels is input.

In the register 27 of the display timing signal clock length detecting section 25, the number of clocks (CK) from the input of the display timing signal (DTMG) to the end of the signal, that is, all pixels of the display data per line are displayed. The number is remembered.

Next, the centering process in the horizontal direction will be described with reference to FIGS.

Here, the value of the register 27 is A, the total number of pixels per one display line of the liquid crystal display panel (LCD) stored in the horizontal section 11 of the display fixed constant section (ROM) 10 is B, and The value of the register 37 is C.

In the comparing section 40, the values of A and B are compared with each other. If the comparison result is A = B, naturally the data processing is not performed and the received display data is directly output to the drain driver 110.

Further, the comparing section 40 compares the values of A and B, and when the comparison result is A <B, the calculating section 50 calculates C-((BA) / 2). And then
The comparison result of the calculation result of the calculation unit 50 and the counter value of the counter 36 of the first display pixel recognition unit 30 is compared in the comparison unit 70, and if they match, the latch clock (D2) to the drain driver 110 is output.

That is, as shown in FIG. 6, the Cth clock (CK), that is, (B-A) / 2 clocks before the first display pixel for displaying the display data on one display line. The latch clock (D2) to the drain driver 110 is output from the − ((BA) / 2) th clock.

From here, until the display data of the first display pixel is input, the black display data is output to the drain driver 110 so that the liquid crystal display panel (LCD) displays black.

Further, the display data transmitted from the main body computer is output to the drain driver 110 from the first display pixel to A pixels.

Further, the display data of black is output to the drain driver 110 for the pixels after the A pixels, and black is displayed on the liquid crystal display panel (LCD).

In FIG. 6, the black display data after A pixels are latched in the drain driver 110 by the latch clock (D2) to the drain driver 110 in the next display line. The drain driver 11 that latches the black display data after A pixels when the comparison result in the section 40 is A <B
The latch clock (D2) to 0 is not shown,
The present invention is not limited to this, and a latch clock (D2) for latching black display data after A pixels may be output.

By the above-mentioned centering process, the display data is moved to the center of the liquid crystal display panel (LCD), so that the display screen can be easily viewed.

Next, the horizontal thinning process will be described.

In the comparison unit 40, the values of A and B are compared, and if the comparison result is A> B, the calculation unit 60 calculates A / (A−B), and this calculation unit 60
And the counter 96 of the thinning line counter section
The counter value is compared with the counter value in the comparison unit 80, and if they match, the latch clock (D
Stop the pulse of 2) once.

That is, at every A / (AB) clock interval, the display data for (AB) pixels is removed and output to the drain driver 110.

As a result, the display data becomes B pixels per line, and all the display data is displayed on the liquid crystal front panel (LCD).

Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

[0111]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) According to the present invention, when the number of display pixels of the display section of the display device does not match the number of display pixels of the display data transmitted from the main body computer or the like, the display data amount is judged. By moving the display screen and performing data processing, it is possible to make the display data displayed on the display unit of the display device easy to see.

As a result, it is possible to provide a versatile display device.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of a centering circuit and a thinning circuit in a display control device of a liquid crystal display device which is an embodiment (embodiment 1) of the present invention.

FIG. 2 is a diagram showing a time chart of a display control signal from the main body computer shown in FIG. 1 and a display control signal generated by the display control device.

FIG. 3 is a diagram showing a display result of a liquid crystal display panel (LCD) when centering is performed, in comparison with a case where centering is not performed.

FIG. 4 is a block diagram showing a circuit configuration of a centering circuit in a display control device of a liquid crystal display device which is another embodiment (embodiment 2) of the present invention.

FIG. 5 is a block diagram showing a circuit configuration of a centering circuit and a thinning circuit in a display control device of a liquid crystal display device which is another embodiment (third embodiment) of the present invention.

6 is a diagram showing a time chart of a display control signal from the main body computer shown in FIG. 5 and a display control signal generated by the display control device.

FIG. 7 is a block diagram showing a schematic configuration of a conventional TFT liquid crystal display device.

8 is a diagram showing a timing chart of a display control signal from the main body computer shown in FIG. 7 and a display control signal generated by the display control device.

[Explanation of symbols]

LCD: liquid crystal display panel, TFT thin film: transistor,
10: Display fixed constant number section (ROM), 20: Display timing signal pulse counting section 21, 21
6, 31, 36, 91, 96 ... Counter, 22, 27,
32, 37 ... Register, 25 ... Display timing signal clock length detecting unit, 30 ... First display line recognizing unit,
35 ... 1st display pixel recognition part, 40, 70, 80 ... Comparison part, 41 ... Left shift circuit, 41 ... Selector 50, 60 ...
Arithmetic unit, 71 ... OR circuit, 90 ... thinning line counter, 95 ... thinning counter, 100 ... display control device,
110 ... Drain driver, 120 ... Gate driver.

Claims (5)

[Claims] 1. A display device, comprising: a display unit; and a display control circuit for driving the display unit based on display data from the main body unit and a display control signal including at least a display timing signal. Is a pulse counting unit for counting the number of pulses of the display timing signal from the main body unit within one frame period, and a comparing unit for comparing the number of pulses counted by the pulse counting unit with the total number of display lines of the display unit. And when the number of pulses counted by the pulse counting unit based on the comparison result of the comparing unit is less than the total number of display lines of the display unit, the display data from the main body unit is moved in a direction perpendicular to the display line. Centering circuit for displaying the display data at the center of the display unit. A display device comprising. 2. The display device according to claim 1, wherein the display control circuit further comprises a display data copying circuit for increasing the display data by copying the display data from the main body at least once. 3. A display device, comprising: a display unit; and a display control circuit for driving the display unit based on display data from the main body unit and a display control signal including at least a display timing signal. Is a pulse counting unit for counting the number of pulses of the display timing signal from the main body unit within one frame period, and a comparing unit for comparing the number of pulses counted by the pulse counting unit with the total number of display lines of the display unit. When the number of pulses counted by the pulse counting unit based on the comparison result of the comparing unit is larger than the total number of display lines of the display unit, the display data from the main body unit is thinned out every predetermined display line to obtain display data. A display device comprising a thinning circuit for displaying. 4. A display device comprising: a display section; a display control circuit for driving the display section based on display data from the main body section and a display control signal including at least a clock signal and a display timing signal; The display control circuit counts the number of pulses of the clock signal from the main body within the valid period of the display timing signal from the main body, the pulse count counted by the pulse count unit, and one of the display unit. When the number of pulses counted by the pulse count unit based on the comparison result of the comparison unit and the total number of pixels per display line is less than the total number of pixels per display line of the display unit, The display data from the main unit is moved horizontally to the display line to And a centering circuit that displays the data in the center of the display unit. 5. A display device comprising a display section, a display control circuit for driving the display section based on display data from the main body section, and a display control signal including at least a clock signal and a display timing signal, The display control circuit counts the number of pulses of the clock signal from the main body within the valid period of the display timing signal from the main body, the pulse count counted by the pulse count unit, and one of the display unit. A comparison unit that compares the total number of pixels per display line, and if the number of pulses counted by the pulse counting unit based on the comparison result of the comparison unit is greater than the total number of pixels per display line of the display unit, Display data per line of display data from the main body is thinned out for each predetermined pixel And a thinning circuit for displaying display data.