JPH07147659A - Driving circuit for liquid crystal panel - Google Patents

Abstract

PURPOSE:To provide a driving circuit for a liquid crystal panel which drives the whole liquid crystal panel when it displays the video signals of lower image resolution compared with the number of pixels of the liquid crystal panel. CONSTITUTION:A timing control circuit 13 receives the horizontal and vertical synchronizing signals and produces the drive clocks for a data driver 11 and a gate driver 12. At this time, the circuit 13 changes the drive clock frequency between a valid video period and a flyback period. Namely, the drive clock frequency is set at a level higher in the flyback period than in the valid video period. As a result, the pixels are driven at a high speed in an area where the video signals are not displayed. Then the whole liquid crystal panel is driven.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal panel drive circuit, and more particularly to a drive system for a driver IC that drives a liquid crystal panel.

[0002]

2. Description of the Related Art First, a liquid crystal panel will be outlined with reference to FIG.

As shown, the liquid crystal panel 11 has a panel surface 1
1a, and this panel surface is provided with a plurality of video data lines (data electrodes) D1 to Dm (m is an integer of 2 or more) and scanning lines (gate electrodes) S1 to Sn (n is an integer of 2 or more). Has been. As such a liquid crystal panel 11, for example, when driving a liquid crystal panel having a pixel number of 1280 dots in the horizontal direction and 1024 dots in the vertical direction, 1
It requires 280 data lines and 1024 scan lines. That is, it is necessary to prepare liquid crystal panels with m = 1280 and n = 1024.

Here, referring also to FIG. 5, the data electrode D1
To Dm are connected to a data driver (not shown), the gate electrodes S1 to Sn are connected to a gate driver (not shown), and a drive timing signal is given to the data driver and the gate driver. A video signal is added to the data driver. The drive timing signal is generated based on the horizontal sync signal Hsync and the vertical sync signal Vsync. The drive clock SCLK is given to the data driver as a drive timing signal,
A drive clock GCLK is given to the gate driver as a drive timing signal.

As a result, a gate applied voltage is applied to the gate electrodes S1 to Sn at every horizontal scanning period, and the gate electrodes S1 to Sn are sequentially selected one by one. On the other hand, a data voltage is applied to the data electrodes D1 to Dm in one horizontal cycle. That is, the data voltage Di (the voltage of the i-th data electrode) is applied to the data electrode Di every horizontal period. Therefore, dots are displayed on the panel according to the data voltage in the gate electrode selected as described above.

Here, referring to FIG. 6 and FIG.
A liquid crystal panel (FIG. 6) composed of (280 dots) × (1024 dots vertically) (1024 dots horizontally) × 768 pixels vertically
When displaying a video signal with a resolution of (dot),
Since the resolution of the input video signal is smaller than the number of pixels of the liquid crystal panel in both the vertical direction and the horizontal direction, an area not involved in the display is formed on the display screen (FIG. 7). When a so-called normally white liquid crystal panel (a liquid crystal panel in which the screen turns white when no voltage is applied) is used as the liquid crystal panel, a voltage non-applied area occurs in the panel, and the area is white. Then, the screen becomes difficult to see.

[0007]

In order to prevent such a problem, a black level data voltage may be applied to a region that is not involved in displaying an effective image. At this time, the data voltage for black level display is applied during the time for returning to the scanning start position, that is, during the blanking period. For example, if the black level display of 256 lines in the extra area in the vertical direction is performed at the same speed as the video effective period, the scanning time is insufficient and the black level data voltage cannot be applied to the extra area within the blanking period. That is, it is necessary to process the area that is not involved in the display within the blanking period of the input video signal, but it is difficult for the conventional liquid crystal panel drive circuit to perform the processing within the blanking period.

It is an object of the present invention to provide a liquid crystal panel drive circuit capable of driving the entire liquid crystal panel when displaying a video signal having a resolution lower than the number of pixels of the liquid crystal panel.

[0009]

According to the present invention, a video signal having a resolution smaller than the number of pixels is displayed on a liquid crystal panel having a predetermined number of pixels, and the video signal is a video valid period. And a blanking period, and a data driver that receives the video signal and applies a data voltage to the liquid crystal panel, a gate driver that applies a gate voltage to the liquid crystal panel, and drive clocks for the data driver and the gate driver, respectively. A liquid crystal panel drive circuit, wherein the timing control means sets the frequency of the drive clock higher than the drive clock frequency in the video valid period in the blanking period. It is desirable to provide a black level signal to the data driver during the blanking period.

[0010]

EXAMPLES The present invention will be described below with reference to examples.

Referring to FIG. 1, the illustrated liquid crystal panel drive circuit includes a data driver 11, a gate driver 12, and a timing control circuit 13. The data driver 11 and the gate driver 12 have data electrodes as described above. And the gate electrode is connected to the liquid crystal panel 14. The data driver 11 is connected to the video signal input terminal 15, and the video signal is supplied from the video signal input terminal 15 to the data driver 11. First and second input terminals 21 and 22 are connected to the timing control circuit 13, and a horizontal synchronizing signal Hsync and a vertical synchronizing signal Vsync are supplied to the timing control circuit 13 from the first and second input terminals 21 and 22, respectively. Given. Then, the timing control circuit 13 supplies the data driver 11 and the gate driver 12 with the data clock signal SCLK and the gate clock signal GCLK.

Now, the number of pixels of the liquid crystal panel 14 is (horizontal 12
When 80 dots) x (1024 dots vertically), (1 horizontal)
The operation of displaying a video signal of 024 dots) × (768 dots vertically) on the liquid crystal panel 14 will be described.

Referring also to FIG. 2, the timing control circuit 13 is supplied with the horizontal synchronizing signal Hsync and the vertical synchronizing signal Vsync as described above. The timing control circuit 13 receives the data clock signal SCLK and the gate clock signal GCLK based on the horizontal synchronizing signal Hsync and the vertical synchronizing signal Vsync.
To generate. That is, in the video effective period, the timing control circuit 13 sets the frequency of the gate clock signal GCLK to be the same as the clock rate of the input video signal. That is,
The timing control circuit 13 sets the frequency of the gate clock signal GCLK to the same frequency as the horizontal synchronizing frequency (or the vertical synchronizing frequency) during the video valid period. On the other hand, in the blanking period, the timing control circuit 13 sets the frequency of the gate clock signal GCLK to a preset high-speed frequency (high-speed frequency> horizontal synchronization frequency). Similarly, the timing control circuit 13 sets the frequency of the data clock signal SCLK to the same frequency as the horizontal synchronizing frequency during the video valid period. On the other hand, in the blanking period, the timing control circuit 13 causes the data clock signal SC
The frequency of LK is set to a preset high speed frequency (high speed frequency> horizontal synchronization frequency). At this time, the black level is given to the data driver 11 as a video signal during the blanking period.

As described above, the timing control circuit 13
By controlling the frequencies of the data clock signal SCLK and the gate clock signal GCLK by the data driver 11,
The data voltage is output from the data line D1 in the order of the first row, the second row, ... And the video signal is displayed. On the other hand, in the blanking period, the frequencies of the data clock signal SCLK and the gate clock signal GCLK are set to high speed, and a black level is given to the data driver 11 as a video signal. As a result, black is displayed in the area where the image is not displayed. That is, as shown in FIG.
The image and black level will be displayed on the screen (see Fig. 3
, The white area represents the image display portion, and the black portion represents the black level display).

As described above, in both the horizontal and vertical directions, the driving clock of each driver is made high in the video ineffective period (retrace line period) to supply a black level as a video signal. When displaying an input video signal having a resolution smaller than a certain number on the liquid crystal panel, all pixels of the liquid crystal panel can be driven, and as a result, natural display can be performed.

[0016]

As described above, according to the present invention, all the pixels of the liquid crystal panel are driven when an input signal having a resolution smaller than the number of pixels of the liquid crystal panel is displayed. There is an effect that can be removed.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating an embodiment of a liquid crystal panel drive circuit according to the present invention.

FIG. 2 is a signal diagram for explaining the operation of the timing control circuit shown in FIG.

FIG. 3 is a diagram showing a display example of a liquid crystal panel when a liquid crystal panel drive circuit according to the present invention is used.

FIG. 4 is a diagram illustrating a configuration of a liquid crystal panel.

FIG. 5 is a signal diagram for explaining the operation of a conventional liquid crystal panel drive circuit.

[FIG. 6] (1280 dots horizontally) × (1024 dots vertically)
It is a figure which shows the liquid crystal panel of.

FIG. 7 is a diagram showing a display example of a liquid crystal panel when a conventional liquid crystal panel drive circuit is used.

[Explanation of symbols]

 11 data driver 12 gate driver 13 timing control circuit 14 liquid crystal panel 15 video signal input terminal 21 first input terminal 22 second input terminal

Claims (3)

[Claims] 1. A liquid crystal panel having a predetermined number of pixels, which is used when displaying a video signal having a resolution smaller than the number of pixels, the video signal having a video valid period and a blanking period. A data driver that receives a video signal and applies a data voltage to the liquid crystal panel; a gate driver that applies a gate voltage to the liquid crystal panel; and a timing control unit that applies a drive clock to the data driver and the gate driver, respectively. The liquid crystal panel drive circuit, wherein the timing control means makes the frequency of the drive clock higher than the drive clock frequency in the video valid period in the blanking period. 2. The liquid crystal panel drive circuit according to claim 1, wherein the timing control means is provided with a horizontal synchronization signal and a vertical synchronization signal of the video signal, and the timing control means includes the horizontal synchronization signal and the vertical synchronization signal. A liquid crystal panel drive circuit, wherein the drive clock is generated based on a vertical synchronization signal. 3. The liquid crystal panel drive circuit according to claim 2, wherein a black level signal is applied to the data driver during the return period.