KR100318384B1 - Liquid crystal display and method of operating the same - Google Patents

Abstract

It is designed to provide a liquid crystal display device and a driving method thereof, which can be driven at a low clock speed to suppress the generation of electromagnetic waves and noise, improve the resolution and contrast of the display screen, and provide a fast response speed. And a timing control circuit for outputting a signal required for driving the source driver including a LOAD signal and a clock signal, and a signal required for driving the gate driver including a gate clock signal and a frame start signal, from the timing control circuit. Provided is a STN liquid crystal display device having a line buffer for receiving signals required for driving and dividing the signals into a plurality of signal sets.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY AND METHOD OF OPERATING THE SAME}

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display and a driving method thereof, and more particularly, to a liquid crystal display and a driving method thereof having a high resolution and contrast and a fast response speed while being driven at a low clock speed.

[Prior art]

In general, a super twisted nematic (STN) liquid crystal display is a liquid crystal layer formed between a segment electrode and a common electrode, and a pixel point is formed by two overlapping electrode terminals. The driving method of the STN liquid crystal display will be described with reference to the accompanying drawings. FIG. 1 is a circuit diagram showing an example of a conventional STN liquid crystal display device, wherein the STN liquid crystal display device has a signal on a panel 10 formed of a common electrode and a segment electrode forming a plurality of pixels, and a segment electrode constituting each pixel. A source driver 20 for applying a voltage and a gate driver 30 and a timing control circuit 40 for sequentially scanning the common electrode so that a specific voltage value can be applied to the pixel are included. The timing control circuit 40 is an Hsync (horizontal synchronization signal) for distinguishing R, G, and B data signals and lines from a graphic controller (not shown) of the computer main body, and a Vsync (vertical synchronization signal) for distinguishing each frame. And a signal for controlling the source driver 20 and the gate driver 40. That is, the timing control circuit 40 inputs the R, G, and B data signals for each segment electrode to the source driver 20 while sequentially shifting according to a predetermined clock speed, and the R, G, and B data signals. When all of the signals are input, the LOAD signal is generated and output to instruct the application of the voltage value corresponding to the data signal to the segment electrode of the panel 10. In addition, the timing control circuit 40 may include a gate clock signal and a frame start signal so that the gate driver 30 may sequentially scan the common electrode of the panel 10 while being synchronized with the source driver 20. The signal is supplied to the gate driver 30. That is, the gate driver 30 has a function of periodically scanning the common electrode to form a constant potential difference in the pixel of the panel 10 together with the analog voltage value applied from the source driver 20.

The source driver 20, also called a data driver, stores a digital data from the timing control circuit 40 in a shift register in the source driver 20, and then a LOAD signal for instructing the panel 10 to lower the data. Then, a voltage corresponding to each data is selected and applied to the panel 10. As shown in FIG. 2, the internal configuration of the source driver 20 generally includes a plurality of shift registers 22 and gray voltages that sequentially store the R, G, and B data output from the timing control circuit 40. A digital / analog converter 24 for converting the R, G, and B data into analog values corresponding to the respective digital data by receiving V ₀ -V _n ), and the converted voltage value, When the LOAD signal is applied from 40), it consists of a latch 26 which is sprayed to the panel 10 immediately. The shift register 22 stores digital data one by one while repeating an operation of simultaneously receiving and shifting three R, G, and B data in one clock cycle. As such, when the first shift register 22 is filled with data, a carry out signal is sent to the next shift register, and the next shift register repeats the same operation to receive data. In this way, when all the source drivers are filled, that is, when all of the horizontal line data has been stored, the data is changed to the analog voltage corresponding to the data code value. The voltage value is applied.

The STN liquid crystal display device does not operate each pixel by an independent terminal, but drives the overlapping portion of the panel 10 while sequentially supplying signals to the segment electrode and the common electrode. The display quality, such as response speed, is not only lower than that of an active matrix liquid crystal display, but also difficult to enlarge a screen or increase a resolution. In order to solve this problem, it is necessary to increase the frequency (clock speed) of the operation signals. For example, to drive a frame of a QVGA (320X240) LCD (using a 12-bit interface) at a frequency of 100 Hz (10 ms), the driving frequency for driving the common electrode is 24 KHz (that is, the time for driving one common electrode). 10 ms / 240 = 41.7 μs = 24 KHz, and the driving frequency for driving the segment electrode is 1.92 MHz (that is, the time for driving one segment electrode is 41.7 μs / 320X3 / 12 = 0.52 μs = 1.92 MHz). Should be. However, if you want to drive one frame of XGA (1024X768) LCD (using 12-bit interface) at 100Hz (10ms) by dual scan method to increase resolution, drive frequency for driving common electrode is 38.5KHz (i.e. The driving time of the common electrode should be increased to 10ms / 384 = 26μs = 38.5KHz, and the driving frequency for driving the segment electrode is 10MHz (ie, the driving time of one segment electrode is 26μs / 1024X3 / 12 = 0.1μs). = 10 MHz).

As described above, increasing the operating frequency is not only difficult to design the circuit, but also has a disadvantage in that a large amount of EMI (Electro-Magnetic Interference) emission is generated according to the operating frequency and a large amount of noise is generated. EMI is a kind of electromagnetic wave, which is harmful to human body. Recently, the regulation has been tightened, and shielding measures have been taken to block it. However, if the operating frequency is 65MHz or higher, it is known that the current technology cannot completely block EMI. . Therefore, in order to increase the screen size while lowering the operating frequency, a method of arranging the source lines 20 at the top and bottom of the panel so that the signal lines cross each other at the upper and lower sides has been developed. There is a disadvantage that the size increases.

Accordingly, an object of the present invention is to provide an STN liquid crystal display device and a driving method thereof, which can be driven at a low clock speed to suppress the generation of electromagnetic waves and noise.

Another object of the present invention is to provide a liquid crystal display and a method of driving the same, wherein the resolution and contrast of the display screen are improved and the response speed is high.

Another object of the present invention is to provide an efficient driving method of a large liquid crystal display.

1 is a block diagram of a conventional STN liquid crystal display device.

Fig. 2 is a block diagram of a source driver used in a conventional STN liquid crystal display device.

3 is a block diagram illustrating an STN liquid crystal display device according to an exemplary embodiment of the present invention.

In order to achieve the above object, the present invention is required for driving a gate driver including a gate clock signal and a frame start signal, a signal required for driving a source driver including an R, G, B data signal, a LOAD signal, and a clock signal. A timing control circuit for outputting a signal and a line buffer for receiving a signal required for driving a source driver from the timing control circuit and dividing the signal into a plurality of signal sets are provided. The liquid crystal display receives the plurality of signal sets, respectively, and drives a gate driver from the source driver and the timing control circuit to supply voltages corresponding to R, G, and B data signals to the segment electrodes of the panel. A gate driver for receiving a signal required to scan the common electrode of the panel further comprises.

The present invention also includes receiving a signal necessary for driving a source driver including an R, G, B data signal, a LOAD signal and a clock signal, and a signal required for driving a gate driver including a gate clock signal and a frame start signal; Receiving a signal for driving the source driver and dividing the signal into a plurality of signal sets to output the signal; And receiving the plurality of signal sets, supplying voltages corresponding to the R, G, and B data signals to the segment electrodes of the panel, and receiving the signals required to drive the gate driver to scan the common electrodes of the panel. It provides a driving method of the STN liquid crystal display device comprising the step of displaying an image.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram illustrating an STN liquid crystal display device according to an embodiment of the present invention. The STN liquid crystal display device of the present invention displays an image and includes a panel 120 in which a plurality of segment electrodes and a common electrode cross each other. The timing control circuit 140 includes a line buffer 112, first to fourth source drivers 122, 124, 126, and 128, and a gate driver 130. The timing control circuit 140 provides a line buffer 112 with a signal necessary for driving the first to fourth source drivers 122, 124, 126, and 128 such as an R, G, and B data signal, a LOAD signal, and a clock signal for each segment electrode. When the R, G, and B data signals are all input to the first to fourth source drivers 122, 124, 126, and 128, the LOAD signal outputs a voltage value from the source driver corresponding to the data signal. It is provided to apply to. In addition, the timing control circuit 140 may include a gate clock so that the gate driver 130 may sequentially scan the common electrode of the panel 120 while being synchronized with the first to fourth source drivers 122, 124, 126, and 128. Signals required for driving the gate driver, such as a (GATE CLOCK) signal and a frame start signal, are supplied to the gate driver 130. The line buffer 112 receives the R, G, and B data signals and the LOAD signal from the timing control circuit 140 through a high speed serial bus or a parallel bus, and the R, G, and B data signals. Is divided into four (first to fourth R, G, and B data) and supplied to the source drivers 122, 124, 126, and 128, respectively. As such, when the R, G, and B data signals are simultaneously supplied to the first to fourth source drivers 122, 124, 126, and 128 using the line buffer 112, the clock speed for supplying the data signals is 4 minutes. It can be strange as 1

For example, when driving an SXGA liquid crystal display (using a 12-bit interface) having 1280 X 1024 pixels at a frame frequency of 100 Hz, a driving frequency for driving the common electrode in a dual scan method is 52.6 KHz (that is, one The driving time of the common electrode is 10ms / 512 = 19μs = 52.6KHz, and the driving frequency for driving the segment electrode without dividing the source driver is 16.7MHz (that is, the driving time of one segment electrode is 19μs / 1280X3 / 12 = 0.06μs = 1.92MHz), but as shown in the present invention, if the source driver is divided into four to drive segment electrodes, the driving frequency at this time is 4.17MHz (that is, the time for driving one segment electrode is 19μs / 320X3 / 12 = 0.24μs = 4.17MHz), driving frequency can be reduced to one quarter.

The line buffer 112 is provided from the first line buffer 114 and the first line buffer 114 to temporarily receive the R, G, and B data signals from the timing control circuit 140 in series or in parallel. The second line buffer 116 may be configured to receive the R, G, and B data signals through a parallel bus, divide them, and transmit the divided data signals to respective source drivers. When the data signal of one line is transmitted to the line buffer 116, the first line buffer 114 receives the data of the next line so that the input and output of data is possible by separating and utilizing time. That is, the first line butter 114 functions as a data input buffer, and the second line buffer 116 functions as a data output buffer.

In this case, the number of divisions of the R, G, and B data signals varies depending on the resolution of the liquid crystal display, but it is preferable to divide the data into even numbers. More preferably, the data is divided into two or four data sets. As many source drivers as there are R, G, and B data signals are provided in the panel 120 of the liquid crystal display.

The gate driver 130 used in the liquid crystal display of the present invention can use all known driver circuits, but it is preferable to use a dual scan driver circuit.

Hereinafter, the operation of the STN liquid crystal display device of the present invention will be described.

First, the computer's central processing unit outputs R, G, and B data signals to a graphics controller (not shown). ) And a clock signal are generated and output to the timing controller 140. The timing controller 140 divides the R, G, and B data signals to meet the required timing, sequentially outputs the LOAD signal to the first line buffer 114 together with the LOAD signal, and also gates the gate driver 130 to drive the gate driver 130. A FRAME START signal for distinguishing the clock signal from the GATE CLOCK and a frame of the screen is output to the gate driver 130.

When all of the R, G, and B data signals corresponding to one common electrode are input to the first line buffer 114, the first line buffer receives the R, G, and B data signals through a parallel bus. 116), and receives R, G, and B data signals corresponding to the next common electrode. In this case, the second line buffer 116 divides the R, G, and B data signals inputted from the first line buffer into four and first through fourth source drivers 122, 124, 126, and 128 through respective parallel buses. To each. As such, when the first to fourth source drivers 122, 124, 126, and 128 receive all data for one line, the LOAD signal is output from the second line buffer 116 and R, to the segment electrode of the panel 120. G and B data signals are applied to display an image. As such, when the R, G, and B data signals are simultaneously supplied to the first to fourth source drivers 122, 124, 126, and 128 using the line buffer 112, the clock speed for supplying the data signals is 4 minutes. It can be strange as 1

The method of driving the STN liquid crystal display device of the present invention can be easily applied not only to a liquid crystal display device that sequentially selects scan electrodes, but also to a multi-line addressing (MULTI LINE ADDRESSING) liquid crystal display device that simultaneously addresses a plurality of lines (segment electrodes). The common electrode can be driven using all the conventional driving methods such as the dual scan method.

When the STN liquid crystal display device driving method of the present invention is used, a large-scale color liquid crystal display device such as SVGA, XGA, SXGA, etc. is divided into QVGA or VGA driving timings, thereby achieving VGA-class liquid crystal having a contrast of 30: 1 and a response speed of 80 ms. It can be driven like a display device. In addition, by adding only two line buffers, the screen of the liquid crystal display device can be easily enlarged without increasing the clock speed, and the driver circuit can be simplified since it is driven at a low clock speed.

Claims (6)

(Correction) a panel in which a plurality of segment electrodes and a common electrode cross each other; A timing control circuit for outputting a signal required for driving the source driver including the R, G, and B data signals, a LOAD signal, and a clock signal, and a signal required for driving the gate driver including the gate clock signal and the frame start signal; And a gate driver configured to scan a common electrode of the panel by receiving a signal necessary for driving a source driver from the timing control circuit. The first line buffer receives the signals necessary for driving the source driver from the timing control circuit and temporarily stores the signals required for driving the source driver from the first line buffer, and divides them into the plurality of source drivers. A line buffer comprising a second line buffer to transmit; And a plurality of source drivers for receiving the plurality of signal sets, respectively, and supplying voltages corresponding to the R, G, and B data signals to the segment electrodes of the panel. (delete) (Correction) The method of claim 1 , wherein the first line buffer transmits a signal for driving a pixel corresponding to a common electrode of one line to the second line buffer, and then selects a pixel corresponding to a common electrode of a next line. STN liquid crystal display device characterized in that it receives a signal for driving. The STN liquid crystal display device according to claim 1, wherein the plurality of source drivers are four, and signals necessary for driving the source driver are divided into four. The liquid crystal display of claim 1, wherein the source driver is configured to simultaneously address a plurality of adjacent segment electrodes. (Correction) receiving a signal required for driving a source driver including an R, G, B data signal, a LOAD signal, and a clock signal, and a signal required for driving a gate driver including a gate clock signal and a frame start signal; After receiving the signals necessary for driving the source driver from the first line buffer and temporarily storing them, the signals required for driving the source driver are received from the first line buffer and divided into a plurality of signal sets in the second line butter. Outputting to a plurality of source drivers; And The plurality of signal sets are input to each other, and voltages corresponding to the R, G, and B data signals are supplied to the segment electrodes of the panel, and the signals required to drive the gate driver are input to scan the common electrodes of the panel. A method of driving an STN liquid crystal display device comprising displaying an image.