KR100922795B1 - Liquid Crystal display Device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display device in which data signals can be applied to all data lines of a liquid crystal panel by one source driver IC. A liquid crystal panel having a data line, a source driver IC for sequentially outputting the n data signals for each group, a counter for counting the data signal output for each group, and an output of the counter are applied to the data line of the selected group. And a decoder for applying the enable signal.

Source Driver IC, Decoder, Counter, Carry Signal, and Scan Line Selection Cycle

Description

Liquid crystal display device

1 is a schematic diagram illustrating a connection relationship between a general liquid crystal panel, a gate, and a source driver.

2 is a schematic diagram showing a connection relationship between a source driver and a data line of a conventional liquid crystal display;

3 is a block diagram illustrating an internal structure of a source driver of FIG. 2.

4A and 4B are block diagrams illustrating a timing diagram and signal transmission of a source driver of a conventional liquid crystal display.

5 is a timing diagram illustrating a relationship between an input carry signal and a buffer control signal of a source driver of a conventional liquid crystal display.

6 is a schematic diagram showing a source driver of a liquid crystal display of the present invention.

7 is a circuit diagram illustrating a data line signal applying unit of the liquid crystal display of the present invention.

8 is a block diagram showing an internal structure of a source driver IC of the liquid crystal display of the present invention.

9 is a timing diagram showing an input carry cycle applied to a source driver IC of the liquid crystal display of the present invention.                 

10 is a block diagram showing signal transmission of a source driver IC of the liquid crystal display of the present invention.

11 is a timing diagram showing a relationship between an input carry signal and a buffer output control signal of a source driver IC of the liquid crystal display of the present invention;

* Description of symbols on the main parts of the drawings *

81: shift register 82: first latch portion

83: second latch portion 84: digital-to-analog conversion portion

85: buffer 86: counter

87 decoder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device which makes it possible to apply a data signal to all data lines configured in a liquid crystal panel with one source driver IC.

As the information society develops, the demand for display devices is increasing in various forms, and in recent years, liquid crystal display devices (LCDs), plasma display panels (PDPs), electro luminescent displays (ELD), and vacuum fluorescent (VFD) Various flat panel display devices such as displays have been studied, and some of them are already used as display devices in various devices.                         

Among them, LCD is the most widely used as the substitute for CRT (Cathode Ray Tube) for mobile image display device because of its excellent image quality, light weight, thinness, and low power consumption. In addition to the use of the present invention has been developed in various ways such as a television and a computer monitor for receiving and displaying broadcast signals.

In order to use such a liquid crystal display as a general screen display device in various parts, it is a matter of how high quality images such as high definition, high brightness and large area can be realized while maintaining the characteristics of light weight, thinness and low power consumption. Can be.

A general liquid crystal display device may be largely divided into a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel, wherein the liquid crystal panel includes first and second glass substrates bonded to each other with a predetermined space; It consists of a liquid crystal layer injected between the said 1st, 2nd glass substrate.

Here, the first glass substrate (TFT array substrate) has a plurality of gate lines arranged in one direction at regular intervals, a plurality of data lines arranged at regular intervals in a direction perpendicular to the gate lines, A plurality of pixel electrodes formed in a matrix form in each pixel region defined by crossing a gate line and a data line, and a plurality of thin film transistors switched by signals of the gate line to transfer the signal of the data line to each pixel electrode. Is formed.

The second glass substrate (color filter substrate) includes a light shielding layer for blocking light except for the pixel region, an R, G, and B color filter layer for expressing color color, and a common image for implementing an image. An electrode is formed.

The driving principle of the general liquid crystal display device uses the optical anisotropy and polarization property of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the arrangement of molecules can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal by optical anisotropy, thereby representing image information.

Currently, an active matrix LCD, in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner, is attracting the most attention due to its excellent resolution and ability to implement video.

Hereinafter, a liquid crystal display according to the related art will be described with reference to the accompanying drawings.

1 is a schematic diagram illustrating a connection relationship between a general liquid crystal panel, a gate, and a source driver.

As shown in FIG. 1, a typical liquid crystal panel 1 includes a thin film transistor (TFT) for each pixel, a gate electrode of the thin film transistor is connected to a gate line which is a scan line, and a source electrode of the thin film transistor is connected to a data line which is a signal line. . In order to apply signals to the gate line and the data line, the gate driver IC 5 and the source driver IC 6 connected to the gate PCB (Printed Circuit Board) 3a and the data PCB 3b are respectively TCP (Tape Carrier). Package) is bonded through the films 7a and 7b. In addition, the gate PCB 3a and the data PCB 3b receive a signal through the driver 2 which controls the timing signal and the system clock.

The liquid crystal panel 1 operating under the control of the driver 2 will be briefly described as follows.

When the ON signal is applied to the gate line as the scan line, a channel is formed in the thin film transistor connected to the gate line, and the voltage of the data line as the signal line is applied to the pixel electrode via the source electrode and the drain electrode.

The resolution of a typical liquid crystal display device is determined according to the number of gate lines and data lines. The TFT LCD module cannot use a dot sequential method with a short selection period due to the low mobility of the TFT elements, and is driven by a line scanning method that lengthens the selection period.

In this case, the number of gate lines and data lines configured in the liquid crystal panel differs depending on the resolution, and the driver ICs configuring the gate driver and the source driver IC also vary in the number of outputs depending on the product. To change the resolution.

2 is a schematic diagram illustrating a connection relationship between a source driver and a data line of a conventional liquid crystal display.

As shown in FIG. 2, a conventional liquid crystal display device includes a plurality of source driver ICs as a source driver and applies a data signal to each data line. At this time, each source driver IC 6 is configured to be bonded on the TCP film 7b.

For example, as shown in the figure, in the case of a source driver IC having 480 output pins, 10 (1600ⅹ3 / 480) are required to implement UXGA (1600ⅹ1200).

In this case, each source driver IC applies data signals to 480 data lines, and a carry signal to adjacent source driver ICs to apply data signals to the next 480 data lines.

3 is a block diagram illustrating an internal structure of a source driver of FIG. 2.

As shown in FIG. 3, the source driver receives an input carry and a clock signal CLK applied from a microcomputer, outputs a latch clock, and receives a load signal from the microcomputer in an even mode according to an address. The first and second latch units 32 and 33 for sampling and holding the image signal RGB data for each of the two / odd modes and the gamma power supply and the polarity output signal POL from the microcomputer. A digital-to-analog converter (DAC) 34 for converting digital signals stored in the latch units 32 and 33 into analog signals, and outputs each signal of the digital-to-analog converter 34 for each data line by receiving an analog power source. Which consists of an output buffer 35.

At this time, the shift register 31 includes a shift register section S / R corresponding to one source driver IC, and shifts from the previous shift register section S / R to the next shift register section S / R. The carry signal is applied at the time of application, and the corresponding latch clock of each data line is stored to simultaneously output data signals corresponding to the first data line to the last data line from the output buffer 35.                         

The operation of the source driver will now be described in detail.

That is, dot at a time scanning is performed by latching data of each RGB sequentially received through the shift register 31 in accordance with a dot clock from a microcomputer through the first and second latch units 32 and 33. Change the timing scheme of the line to a time at line scan.

Subsequently, data stored in the first latch unit 32 is transferred to the second latch unit 33 in accordance with a transfer enable signal at every horizontal line period.

Data stored in the second latch unit 33 receives a gamma reference voltage as an operating power source and converts the digital-to-analog converter 34 into an analog voltage in response to a polarity out load (POL) applied from a microcomputer. Is switched.

Subsequently, it is applied to each data line via the output buffer 35 according to the control signal applied from the analog power source and the microcomputer.

4A and 4B are block diagrams illustrating a timing diagram and signal transmission of a source driver of a conventional liquid crystal display.

As shown in FIG. 4A, a source driver of a conventional liquid crystal display device operates according to an input carry signal, and the input carry signal operates one scan line selection time in one period. That is, in response to one input carry signal, a data signal corresponding to all data lines is output to the corresponding scan line.

As shown in FIG. 4B, when a plurality of source driver ICs having 480 output pins are provided, each of the source driver ICs includes a shift register unit S / R, and a signal between each shift register unit S / R. It can be seen that the transfer is made to the carry signal.

A conventional source driver having such a structure, even though a plurality of source driver ICs are provided, is simultaneously transferred through a carry signal between the shift register units (S / R) to store predetermined time image data, and then simultaneously output data signals to all data lines. do.

5 is a timing diagram illustrating a relationship between an input carry signal and a buffer control signal of a source driver of a conventional liquid crystal display.

As shown in FIG. 5, after the input carry signal is applied, image data is stored for all data lines, and when a buffer output control signal is applied, the data signal is simultaneously output through the output buffer corresponding to each data line.

However, the conventional liquid crystal display device as described above has the following problems.

As the number of gate lines and data lines increases as a liquid crystal display device exhibits high resolution, a conventional liquid crystal display device having a driver IC corresponding to each line one to one has a larger number of driver ICs. In particular, the source driver IC is expensive, and in this case, it is difficult to adjust the liquid crystal display device at an appropriate price in response to the increasing source driver IC.

Therefore, efforts have been made to reduce the source driver IC. The present invention has been made to solve the above problems, and the data line structure of the liquid crystal panel is changed to a switching structure, and the control signal for controlling the source driver IC is modified. In addition, by providing an output signal for controlling the switching element of the data line and periodically adjusting the output signal, to provide a source driver and a driving method of the liquid crystal display device that can be driven by one source driver IC, The purpose is.

The liquid crystal display device of the present invention for achieving the above object is a liquid crystal panel having a plurality of groups of data lines when the data line receiving the n number of data signals as a group, and the n data signals by group Source driver IC to sequentially output, a counter for counting the data signal output of each group, and a decoder for receiving the output of the counter to apply the enable signal to the data line of the selected group, characterized by have.

The counter may be counted by receiving a carry signal that is output after the first group of latch clocks are generated from the source driver IC.

Preferably, the decoder applies an enable signal to the source driver IC so that data signals of the source driver IC are applied to data lines of a selection group, respectively.

Preferably, the enable signal is applied at a period of time divided by the number of groups of data lines provided with a scan line selection time.

The data signal input terminal of each data line may be operated by receiving an enable signal of the decoder as a gate signal, and further including a transistor configured to apply a data signal output from the source driver IC during an on operation.

The source driver IC receives a clock signal and an input carry signal applied from a microcomputer, outputs a latch clock corresponding to the selected group, and outputs a carry signal after the latch clock of the selected group is terminated, and a load signal from the microcomputer. First and second latch units for sampling and holding the digital image signal corresponding to the latch clock, and receiving a gamma reference voltage and a polarity signal from a microcomputer to store the digital image signals stored in the first and second latch units. And an output buffer for receiving the enable signal and outputting an analog video signal for each data line of a selected group from the digital analog converter.

The input carry signal is preferably applied in a period of time divided by the number of groups of data lines provided with the scan line selection time.

Preferably, the enable signal is applied at a period of time divided by the number of groups of data lines provided with a scan line selection time.

Hereinafter, a liquid crystal display and a driving method of the present invention will be described in detail with reference to the accompanying drawings.

6 is a schematic view showing a source driver of a liquid crystal display of the present invention.

As illustrated in FIG. 6, the liquid crystal display of the present invention applies signals to a plurality of groups of data lines using a single source driver IC.

Here, the group of data lines means a data line corresponding to the number of output pins of the single source driver IC. That is, the liquid crystal display of the present invention is characterized by including a source driver IC and bus structure of the data line so that data signals are sequentially applied to each group.

The presented figure relates to a UXGA type liquid crystal display device, and has a resolution of 1600 x 1200 and 1600 x 3, that is, 4800 data lines.

Therefore, in this case, when a source driver IC having 480 output pins is used, 10 groups of data lines are configured in the liquid crystal panel, and one source driver IC is operated in correspondence with the 10 groups of data lines. Done.

7 is a circuit diagram illustrating a data line signal applying unit of the liquid crystal display of the present invention.

As illustrated in FIG. 7, each data line of the liquid crystal display of the present invention includes transistors in a signal applying unit, and the transistors receive enable signals TR1, TR2,...

8 is a block diagram showing an internal structure of a source driver IC of the liquid crystal display of the present invention.

As shown in FIG. 8, the source driver of the liquid crystal display according to the present invention receives an input carry and a clock signal CLK applied from a microcomputer and applies a shift register 81 to output a latch clock, and a load signal from the microcomputer. The gamma power supply and the polarity output signal POL from the first and second latch units 82 and 83 and the microcomputer to receive and store the image signals RGB data according to the even mode and the odd mode according to the address. The digital-analog converter 84 converts the digital signals stored in the first and second latch units 82 and 83 into analog signals, and simultaneously receives each signal of the digital-analog converter 84 by receiving an analog power supply. An output buffer 85 for outputting to the signal input terminal of the counter, a counter 86 for counting in response to a carry signal output after completion of the latch clock of the corresponding group of the shift register 81, and the count It comprises a decoder (87) for applying an enable signal to the data lines of the group in accordance with an output state (86).

The operation of the source driver of the liquid crystal display of the present invention will be described in detail as follows.

That is, dot at a time scanning is performed by latching data of each RGB sequentially received through the shift register 81 in accordance with a dot clock from a microcomputer through the first and second latches 82 and 83. Change the timing scheme of the line to a line at a time scanning.

Subsequently, data stored in the first latch unit 82 is transferred to the second latch unit 83 in accordance with a transfer enable signal at every horizontal line period.

The data stored in the second latch unit 83 receives an operating power as a gamma reference voltage and converts the digital-analog converter 84 into an analog voltage in response to a polarity out load (POL) applied from a microcomputer. Is switched.

Then, it is applied to each data line via the output buffer 85 in accordance with the control signal applied from the analog power supply and the microcomputer.

Here, the source driver of the liquid crystal display device of the present invention determines the output of the carry signal output when the group of the shift register 81 is completed, and then determines the output of the counter 86 to sequentially determine the next group. It further includes a decoder 87 for applying the enable signal to the corresponding data line of, thereby acting as a plurality of driver IC through a single source driver IC.

The enable signals TR1, TR2, ... outputted from the decoder 87 are applied to the gate inputs of the transistors configured in the signal applying units of the respective data lines shown in FIG. 7 and simultaneously applied to the data lines of the selected group. The enable signals TR1, TR2, ... are applied to output data signals stored in the output buffer 85.

9 is a timing diagram illustrating an input carry cycle applied to a source driver IC of the liquid crystal display of the present invention.

As illustrated in FIG. 9, the input carry signal applied to the source driver IC of the liquid crystal display of the present invention is applied at a period of 1/10 of one scan line selection period (1 vertical). That is, one input carry signal is applied to each data line of the corresponding group, and the plurality of input carry signals are applied to the plurality of data lines.

For example, in the case of UVGA, 10 input carry signals are applied corresponding to one scan line and corresponding to the group.

10 is a block diagram showing signal transmission of a source driver IC of the liquid crystal display of the present invention.

As shown in FIG. 10, the liquid crystal display of the present invention includes a single source driver IC. Therefore, the shift register 81 stores a latch clock of 480 stages corresponding to the corresponding group, and then outputs a carry signal. The counter 86 ) Counts in response to the carry signal, and receives the power supply voltage Vcc from the system, and sequentially enables enable signals TR1, TR2, ... of the corresponding group according to the output state of the counter 86. Outputs

11 is a timing diagram showing a relationship between an input carry signal and a buffer output control signal of a source driver IC of the liquid crystal display of the present invention;

As shown in FIG. 11, the input carry signal is applied from the system in a period of 1/10 of one scan line selection signal, delays the input carry signal by a predetermined time, and applies buffer output control signals for each group at the same period.

The liquid crystal display of the present invention uses a single source driver IC as a source driver, and further includes a counter and a decoder.

As described above, in order to use a single source driver IC, a corresponding data line of the output pin number of the source driver IC is a group of data lines, a plurality of groups of data lines are provided, and a data line structure on the liquid crystal panel is busified. By changing the data lines connected to each group like branches.

In addition, the liquid crystal display of the present invention counts the groups from 1 to 10 sequentially through a counter, selects data lines of the group, and decodes the gates of the transistors configured in the signal applying unit to each data line for each group. By simultaneously applying the enable signal of the high level (Vcc), the data signal for each selected group is applied.

The liquid crystal display of the present invention as described above has the following effects.                     

A counter and a decoder are added to the liquid crystal display, the data line structure is busified, and a transistor is further configured in the signal applying section of each data line, and one source driver IC is used as one source driver IC in a plurality of data lines. Enable data signal application.

Therefore, the manufacturing cost of the liquid crystal panel can be lowered by reducing the demand for expensive source driver ICs.

Claims (8)

a liquid crystal panel having a plurality of groups of data lines when the data lines to which n data signals are applied are grouped into one group; A source driver IC configured to sequentially output the n data signals for each group; A counter for counting the data signal output for each group; And, And a decoder configured to receive an output of the counter and apply an enable signal to a data line of a selected group. The method of claim 1, And the counter is counted by receiving a carry signal outputted after the first group of latch clocks are generated from the source driver IC. The method of claim 1, And the decoder applies an enable signal to the source driver IC so that data signals of the source driver IC are applied to data lines of a selected group, respectively. The method of claim 1, And the enable signal is applied in a period of time divided by the number of groups of data lines provided with a scan line selection time. The method of claim 1, And a transistor for applying an enable signal of the decoder to a data signal input terminal of each data line as a gate signal, and applying a data signal output from the source driver IC during an on operation. Display device. The method of claim 1, The source driver IC A shift register receiving a clock signal and an input carry signal applied from a microcomputer and outputting a latch clock corresponding to a selection group, and outputting a carry signal after completion of the latch clock of the selection group; First and second latch units receiving a load signal from a microcomputer and sampling and holding a digital video signal in response to the latch clock; A digital-to-analog converter configured to receive a gamma reference voltage and a polarity signal from a microcomputer and convert the digital video signal stored in the first and second latch units into an analog video signal; And an output buffer receiving the enable signal and outputting an analog image signal for each data line of a selected group from the digital analog converter. The method of claim 6, And the input carry signal is applied at a period of time divided by a group of data lines provided with a scan line selection time. The method of claim 6, And the enable signal is applied in a period of time divided by the number of groups of data lines provided with a scan line selection time.

Images