JPS61286879A - Large integrated circuit for crt display - Google Patents

Large integrated circuit for crt display

Info

Publication number
JPS61286879A
JPS61286879A JP60130146A JP13014685A JPS61286879A JP S61286879 A JPS61286879 A JP S61286879A JP 60130146 A JP60130146 A JP 60130146A JP 13014685 A JP13014685 A JP 13014685A JP S61286879 A JPS61286879 A JP S61286879A
Authority
JP
Japan
Prior art keywords
pulse signal
circuit
period
integrated circuit
exclusive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60130146A
Other languages
Japanese (ja)
Inventor
博三 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP60130146A priority Critical patent/JPS61286879A/en
Publication of JPS61286879A publication Critical patent/JPS61286879A/en
Pending legal-status Critical Current

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  • Controls And Circuits For Display Device (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はCRT画面上に数字・文字・図形等を表示させ
るための映像信号を発生し、しかもこれらのキャラクタ
−出力をきわめて鮮明に表示させる事のできるCRT表
示用大規模集積回路に関する0 従来の技術 CRT表示用大規模集積回路は、ブラウン管(CRT)
上に文字を表示するための映像信号を発生する。この映
像信号を生成するための内部ロジック回路を動作させる
ために、基準となるパルス信号(このパルス信号を、以
下「基準パルス信号」と称す。)が必要である。
[Detailed Description of the Invention] Industrial Application Field The present invention is a method for generating video signals for displaying numbers, characters, figures, etc. on a CRT screen, and for displaying these character outputs extremely clearly. 0 Related to large-scale integrated circuits for CRT displays Conventional technology Large-scale integrated circuits for CRT displays are cathode ray tubes (CRTs).
Generates a video signal to display characters on top. In order to operate the internal logic circuit for generating this video signal, a reference pulse signal (this pulse signal is hereinafter referred to as a "reference pulse signal") is required.

従来では、この基準パルス信号を、CRT表示用大規模
集積回路内部のパルス発振回路で直接発振する方法など
で生成していた。
Conventionally, this reference pulse signal has been generated by directly oscillating it in a pulse oscillation circuit inside a large-scale integrated circuit for CRT display.

発明が解決しようとする問題点 このような従来の基準パルス信号の生成方法では、CR
T表示用大規模集積回路をテレビジョン受像機内に装着
した場合、基準パルス信号またはその高調波成分が高周
波ノイズとなり、テレビジョン受像機内の電子回路の信
号に干渉する。
Problems to be Solved by the Invention In such a conventional reference pulse signal generation method, CR
When a large-scale integrated circuit for T display is installed in a television receiver, the reference pulse signal or its harmonic components become high frequency noise and interfere with the signals of the electronic circuits in the television receiver.

また、発振回路には、発振周波数が高くなる程、動作が
不安定になシ、消費電流が増加する傾向がある。
Furthermore, as the oscillation frequency becomes higher, the oscillation circuit tends to operate more unstable and consume more current.

本発明はかかる点に鑑みてなされたもので、基準パルス
信号から発生する高周波ノイズ、および消費電流を効果
的に低減する事を目的としている。
The present invention has been made in view of this point, and an object of the present invention is to effectively reduce high frequency noise generated from a reference pulse signal and current consumption.

問題点を解決するための手段 本発明は、上記問題点を解決するため、CRT表示用大
規模集積回路の内部の発振器で発振するパルス信号の周
期を基準パルス信号の周期の2倍にし、内部で周期を月
にする事により、基準パルス信号から発生する高周波ノ
イズ、および消費電流を低減するものである。
Means for Solving the Problems In order to solve the above problems, the present invention makes the period of the pulse signal oscillated by the oscillator inside the large-scale integrated circuit for CRT display twice the period of the reference pulse signal, and the internal By changing the period to a month, high frequency noise generated from the reference pulse signal and current consumption are reduced.

作  用 本発明は、上記の手段によficRT表示用大規模集積
回路内部の発振器で発振するパルス信号の周期を2倍に
するため、テレビジ87受像機に影響を及ぼす高調波成
分を効果的に低減するとともに、消費電流をも低減でき
る。
Function The present invention doubles the period of the pulse signal oscillated by the oscillator inside the large-scale integrated circuit for ficRT display by the above-mentioned means, thereby effectively eliminating harmonic components that affect the TV87 receiver. At the same time, current consumption can also be reduced.

実施例 第1図は本発明の基準パルス信号発生の一実施例を示す
ブロック図である。第1図において1は基準パルス信号
の2倍の周期をもつパルス信号発振回路、2はパルス信
号の周期を月にするパルス周期制御回路、3は映像信号
発生回路、そして4は映像信号出力端子である。
Embodiment FIG. 1 is a block diagram showing an embodiment of reference pulse signal generation according to the present invention. In Figure 1, 1 is a pulse signal oscillation circuit with a period twice that of the reference pulse signal, 2 is a pulse period control circuit that makes the period of the pulse signal monthly, 3 is a video signal generation circuit, and 4 is a video signal output terminal. It is.

パルス信号発生回路1で発生したパルス信号の周期をパ
ルス信号の周期を%にするパルス周期制御回路2で号に
して基準パルス信号とする。映像信号発生回路3では基
準パルス信号を使用して映像信号を生成し、映像信号出
力端子4より出力する。
The period of the pulse signal generated by the pulse signal generation circuit 1 is converted into a reference pulse signal by a pulse period control circuit 2 which converts the period of the pulse signal into a percentage. The video signal generation circuit 3 generates a video signal using the reference pulse signal and outputs it from the video signal output terminal 4.

ここで第2図および第3図で、第1図のパルス信号の周
期をHにするパルス周期制御回路2の具体例を説明する
Here, a specific example of the pulse period control circuit 2 that changes the period of the pulse signal shown in FIG. 1 to H will be explained with reference to FIGS. 2 and 3.

第2図において、5は入力信号印加端子、6は伝搬遅れ
dtのバッフ1回路、9はエクスクル−シブOR(排他
的論理和9回路である。入力信号印加端子5に第3図の
Aに示したパルス信号を印加した場合、エクスクル−シ
ブOR回路には、エクスクル−シブOR回路の一方の入
力端子7からは入力信号印加端子6に印加したパルス信
号が伝搬遅れ無しに印加されるが、エクスクル−シブO
R回路の他方の入力端子8からはバッファ回路6の伝搬
遅れにより、第3図Bに示したような、時間Δを遅れた
パルス信号が印加される。
In FIG. 2, 5 is an input signal application terminal, 6 is a buffer circuit with a propagation delay dt, and 9 is an exclusive OR (9 exclusive OR circuit).The input signal application terminal 5 is connected to A in FIG. When the shown pulse signal is applied, the pulse signal applied to the input signal application terminal 6 is applied to the exclusive OR circuit from one input terminal 7 of the exclusive OR circuit without propagation delay. Exclusive O
Due to the propagation delay of the buffer circuit 6, a pulse signal delayed by a time Δ as shown in FIG. 3B is applied from the other input terminal 8 of the R circuit.

この時、出力端子1oに現われるエクスクル−シブOR
回路9の出力パルス信号は、第3図Cに示したようにな
シ、このパルス信号の周期は、入力信号印加端子5に印
加したパルス信号の周期のHになる。第3図りは、従来
例のパルス信号発振回路で得られる標準的な基準パルス
信号であり、第3図Cのパルス信号はこの標準的な基準
パルス信号と同じ周期である。
At this time, the exclusive OR appearing at output terminal 1o
The output pulse signal of the circuit 9 is as shown in FIG. 3C, and the period of this pulse signal is H of the period of the pulse signal applied to the input signal application terminal 5. The third diagram shows a standard reference pulse signal obtained by a conventional pulse signal oscillation circuit, and the pulse signal in FIG. 3C has the same period as this standard reference pulse signal.

発明の効果 本発明によると、CRT表示用大規模集積回路内部の発
振回路で生じる発振パルス信号の周期が、映像信号を生
成するた、めの内部ロジック回路を動作させるための基
準パルス信号の周期の2倍であるから、同発振回路から
生じる高調波成分を効果的に低減し、テレビジョン受像
機に影響する高周波ノイズを顕著に低減することができ
る。また、この集積回路によれば、発振回路の発振周波
数の低下に依存して、消費電流も低くすることができる
Effects of the Invention According to the present invention, the period of the oscillation pulse signal generated in the oscillation circuit inside the large-scale integrated circuit for CRT display is equal to the period of the reference pulse signal for operating the internal logic circuit for generating the video signal. Since the frequency is twice that of the oscillation circuit, it is possible to effectively reduce harmonic components generated from the oscillation circuit, and to significantly reduce high frequency noise that affects television receivers. Furthermore, according to this integrated circuit, the current consumption can be reduced depending on the reduction in the oscillation frequency of the oscillation circuit.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の一実施例を示す図、第2図は本発明
のパルス信号制御手段の要部回路図、第δ 3図は要部の動作波形図を示す。 1・・・・・・パルス信号発振回路、2・・・・・・パ
ルス信号の周期を%にするパルス周期制御回路、3・・
・・・・映像信号発生回路、4・・・・・・映像信号出
力端子、5・・・・・・入力信号印加端子、6・・・・
・・バッファ回路、7・・・・・・エクスクル−シブO
R回路(排他的論理和)の入力端子、8・・・・・・エ
クスクル−シブOR回路(排他的論理和)の入力端子、
9・・・・・・エクスクル−シブOR回路(排他的論理
和)、10・・・・・・2人力エクスクルーシブOR回
路(排他的論理和)の出力端子。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第2図 第3図
FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram of the main part of the pulse signal control means of the invention, and FIG. 3 is an operation waveform diagram of the main part. 1...Pulse signal oscillation circuit, 2...Pulse cycle control circuit that changes the cycle of the pulse signal as a percentage, 3...
...Video signal generation circuit, 4...Video signal output terminal, 5...Input signal application terminal, 6...
...Buffer circuit, 7...Exclusive O
Input terminal of R circuit (exclusive OR), 8...Input terminal of exclusive OR circuit (exclusive OR),
9: Exclusive OR circuit (exclusive OR), 10: Output terminal of two-person exclusive OR circuit (exclusive OR). Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 表示信号制御用ロジック回路を動作させるための基準パ
ルス信号を、同基準パルス信号の2倍周期のパルス信号
を発生する発振手段と前記パルス信号を1/2周期化す
る論理手段とにより生成する構成をそなえたCRT表示
用大規模集積回路。
A configuration in which a reference pulse signal for operating a display signal control logic circuit is generated by an oscillation means for generating a pulse signal with a period twice that of the reference pulse signal, and a logic means for halving the period of the pulse signal. A large-scale integrated circuit for CRT display.
JP60130146A 1985-06-14 1985-06-14 Large integrated circuit for crt display Pending JPS61286879A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60130146A JPS61286879A (en) 1985-06-14 1985-06-14 Large integrated circuit for crt display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60130146A JPS61286879A (en) 1985-06-14 1985-06-14 Large integrated circuit for crt display

Publications (1)

Publication Number Publication Date
JPS61286879A true JPS61286879A (en) 1986-12-17

Family

ID=15027069

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60130146A Pending JPS61286879A (en) 1985-06-14 1985-06-14 Large integrated circuit for crt display

Country Status (1)

Country Link
JP (1) JPS61286879A (en)

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