JPS5544271A - Pulse conversion circuit - Google Patents

Pulse conversion circuit

Info

Publication number
JPS5544271A
JPS5544271A JP11769278A JP11769278A JPS5544271A JP S5544271 A JPS5544271 A JP S5544271A JP 11769278 A JP11769278 A JP 11769278A JP 11769278 A JP11769278 A JP 11769278A JP S5544271 A JPS5544271 A JP S5544271A
Authority
JP
Japan
Prior art keywords
circuit
pulse
fed
counter
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11769278A
Other languages
Japanese (ja)
Inventor
Katsumi Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11769278A priority Critical patent/JPS5544271A/en
Publication of JPS5544271A publication Critical patent/JPS5544271A/en
Pending legal-status Critical Current

Links

Landscapes

  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE: To make unnecessary the time constant circuit and to make suitable for circuit integration, by controlling the counter value of the pulse width counter through the use of the converted pulse and determining the width of conversion pulse through the comparison of it with the count value of the reference counter.
CONSTITUTION: The input terminal 21 is connected to the clock circuit 22 and also to the register 24 directly, and the clock pulse or reset pulse produced at the circuit 22 is fed to the pulse width counter 23. Next, the output of the counter 23 is fed to the register 24 and this output is fed to the comparison circuit 28. On the other hand, the input terminal 25 of the reference pulse is banched and connected respectively to the reference clock pulse generation circuit 26, reference counter 27 and inversion circuit 29, and the output of the circuit 26 is fed to the circuit 28 via the circuit 27, and this output is fed to the inversion circuit 29 connected to the output terminal 30. Thus, the pulse P inputted to the terminal 21 is in synchronizing with the horizontal synchronizing signal H fed to the terminal 25 to pick up from the terminal 30 as the dignal Q of different width.
COPYRIGHT: (C)1980,JPO&Japio
JP11769278A 1978-09-25 1978-09-25 Pulse conversion circuit Pending JPS5544271A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11769278A JPS5544271A (en) 1978-09-25 1978-09-25 Pulse conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11769278A JPS5544271A (en) 1978-09-25 1978-09-25 Pulse conversion circuit

Publications (1)

Publication Number Publication Date
JPS5544271A true JPS5544271A (en) 1980-03-28

Family

ID=14717926

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11769278A Pending JPS5544271A (en) 1978-09-25 1978-09-25 Pulse conversion circuit

Country Status (1)

Country Link
JP (1) JPS5544271A (en)

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