JPS5570918A - Digital signal processing unit - Google Patents

Digital signal processing unit

Info

Publication number
JPS5570918A
JPS5570918A JP14305778A JP14305778A JPS5570918A JP S5570918 A JPS5570918 A JP S5570918A JP 14305778 A JP14305778 A JP 14305778A JP 14305778 A JP14305778 A JP 14305778A JP S5570918 A JPS5570918 A JP S5570918A
Authority
JP
Japan
Prior art keywords
write
ram
fed
bit
address signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14305778A
Other languages
Japanese (ja)
Inventor
Kentaro Odaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP14305778A priority Critical patent/JPS5570918A/en
Publication of JPS5570918A publication Critical patent/JPS5570918A/en
Pending legal-status Critical Current

Links

Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Error Detection And Correction (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)

Abstract

PURPOSE: To establish low cost and simple constitution, by using random access memory to the delay unit with interleaving and time axis compression.
CONSTITUTION: When the write-in bit clock RWBC is fed to the write-in address counter 20W of the encoder 7, the bit and word address signal and ROM input signal are produced and they are fed to the selectors 21a, 21b and 21c. The write-in bit and word address signal selected at the selectors 21a and 21b are given to the RAM and ROM input signal selected at the selector 21c is fed to ROM22 to produce the block address signal and to control the block address of RAM. The frequency of the bit clock RRBC for readout is higher than RWBC and the time axis compression is made with the pause for a given period corresponding to the vertical blanking and interleaving is made by RAM. Thus, low cost and simple constitution can be enabled.
COPYRIGHT: (C)1980,JPO&Japio
JP14305778A 1978-11-20 1978-11-20 Digital signal processing unit Pending JPS5570918A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14305778A JPS5570918A (en) 1978-11-20 1978-11-20 Digital signal processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14305778A JPS5570918A (en) 1978-11-20 1978-11-20 Digital signal processing unit

Publications (1)

Publication Number Publication Date
JPS5570918A true JPS5570918A (en) 1980-05-28

Family

ID=15329901

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14305778A Pending JPS5570918A (en) 1978-11-20 1978-11-20 Digital signal processing unit

Country Status (1)

Country Link
JP (1) JPS5570918A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59127445A (en) * 1983-01-10 1984-07-23 Akai Electric Co Ltd Memory access circuit
JPS60213132A (en) * 1984-04-06 1985-10-25 Nec Corp Digital signal processor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59127445A (en) * 1983-01-10 1984-07-23 Akai Electric Co Ltd Memory access circuit
JPS60213132A (en) * 1984-04-06 1985-10-25 Nec Corp Digital signal processor
JPH0352694B2 (en) * 1984-04-06 1991-08-12 Nippon Electric Co

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