JPS5710841A - Interruption address generating circuit - Google Patents

Interruption address generating circuit

Info

Publication number
JPS5710841A
JPS5710841A JP8534380A JP8534380A JPS5710841A JP S5710841 A JPS5710841 A JP S5710841A JP 8534380 A JP8534380 A JP 8534380A JP 8534380 A JP8534380 A JP 8534380A JP S5710841 A JPS5710841 A JP S5710841A
Authority
JP
Japan
Prior art keywords
interruption
address
circuit
generating circuit
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8534380A
Other languages
Japanese (ja)
Other versions
JPS6239777B2 (en
Inventor
Junichi Ishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8534380A priority Critical patent/JPS5710841A/en
Publication of JPS5710841A publication Critical patent/JPS5710841A/en
Publication of JPS6239777B2 publication Critical patent/JPS6239777B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/48Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806Task transfer initiation or dispatching
    • G06F9/4812Task transfer initiation or dispatching by interrupt, e.g. masked

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To generate plural necessary interruption addresses in order by generating one interruption signal, by utilizing a delay effect of a shift register, in an interruption address generating circuit of a sequencer. CONSTITUTION:In a sequencer by which processing is executed in accordance with an address generated from a program counter 1, when an interruption signal B is generated, this signal is latched by a latching circuit 7, and a flip-flop circuit 4 inhibits supply of a clock A to the program counter 1. Flip-flop circuits 5, 6 constitute a 2 bit shift register for delaying an output, and by these outputs D, E, two address (x) and address (y) which are desired to be processed by means of interruption by a selecting circuit 2 are selected and outputted in order.
JP8534380A 1980-06-24 1980-06-24 Interruption address generating circuit Granted JPS5710841A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8534380A JPS5710841A (en) 1980-06-24 1980-06-24 Interruption address generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8534380A JPS5710841A (en) 1980-06-24 1980-06-24 Interruption address generating circuit

Publications (2)

Publication Number Publication Date
JPS5710841A true JPS5710841A (en) 1982-01-20
JPS6239777B2 JPS6239777B2 (en) 1987-08-25

Family

ID=13856001

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8534380A Granted JPS5710841A (en) 1980-06-24 1980-06-24 Interruption address generating circuit

Country Status (1)

Country Link
JP (1) JPS5710841A (en)

Also Published As

Publication number Publication date
JPS6239777B2 (en) 1987-08-25

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