JPS57107031A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57107031A
JPS57107031A JP18474480A JP18474480A JPS57107031A JP S57107031 A JPS57107031 A JP S57107031A JP 18474480 A JP18474480 A JP 18474480A JP 18474480 A JP18474480 A JP 18474480A JP S57107031 A JPS57107031 A JP S57107031A
Authority
JP
Japan
Prior art keywords
polycrystal
inert
layer
substrate
function region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18474480A
Other languages
Japanese (ja)
Inventor
Shuji Tabuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18474480A priority Critical patent/JPS57107031A/en
Publication of JPS57107031A publication Critical patent/JPS57107031A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To suppress a formation of an inert film on the surface by exposing a polycrystal Si layer initially after cooling it gradually in an inert or reducible atmosphere when a semiconductor device is constituted by connecting electrically an Al wiring through the polycrystal Si layer to a function region consisting of a single crystal Si. CONSTITUTION:An insulated film having a contact window responsive to a function region, is provided on a semiconductor substrate having the function region formed thereon previously, and the substrate is accommodated in a conventional polycrystal vapor growth device. Subsequently, SiH4 gas of a predetermined flow is introduced to the device and the temperature of the gas is raised up to 620-650 deg.C and is placed at it is for a predetermined time to grow a polycrystal Si layer of 100-150Angstrom substantially in thickness on the substrate. Thereafter the device is switched to an inert or reducible atmosphere and is cooled gradually 100-200 deg.C and is exposed to the air at a normal temperature. According to such a constitution, when the semiconductor is taken out from the processing device, the inert film is not formed, consequently a connection resistance to the Al wiring formed thereon can be considerably reduced.
JP18474480A 1980-12-25 1980-12-25 Manufacture of semiconductor device Pending JPS57107031A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18474480A JPS57107031A (en) 1980-12-25 1980-12-25 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18474480A JPS57107031A (en) 1980-12-25 1980-12-25 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57107031A true JPS57107031A (en) 1982-07-03

Family

ID=16158580

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18474480A Pending JPS57107031A (en) 1980-12-25 1980-12-25 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57107031A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50140060A (en) * 1974-04-26 1975-11-10

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50140060A (en) * 1974-04-26 1975-11-10

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