JPS57106040A - Prevention of stacking fault - Google Patents

Prevention of stacking fault

Info

Publication number
JPS57106040A
JPS57106040A JP18249580A JP18249580A JPS57106040A JP S57106040 A JPS57106040 A JP S57106040A JP 18249580 A JP18249580 A JP 18249580A JP 18249580 A JP18249580 A JP 18249580A JP S57106040 A JPS57106040 A JP S57106040A
Authority
JP
Japan
Prior art keywords
interstitial
added
stacking fault
c2hcl3
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18249580A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0434299B2 (enExample
Inventor
Takeshi Hattori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP18249580A priority Critical patent/JPS57106040A/ja
Publication of JPS57106040A publication Critical patent/JPS57106040A/ja
Publication of JPH0434299B2 publication Critical patent/JPH0434299B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
JP18249580A 1980-12-22 1980-12-22 Prevention of stacking fault Granted JPS57106040A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18249580A JPS57106040A (en) 1980-12-22 1980-12-22 Prevention of stacking fault

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18249580A JPS57106040A (en) 1980-12-22 1980-12-22 Prevention of stacking fault

Publications (2)

Publication Number Publication Date
JPS57106040A true JPS57106040A (en) 1982-07-01
JPH0434299B2 JPH0434299B2 (enExample) 1992-06-05

Family

ID=16119280

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18249580A Granted JPS57106040A (en) 1980-12-22 1980-12-22 Prevention of stacking fault

Country Status (1)

Country Link
JP (1) JPS57106040A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05145027A (ja) * 1990-12-21 1993-06-11 Siliconix Inc シリコン集積回路の製造に於ける欠陥形成の制御方法、酸化膜の品質及び欠陥形成の制御方法、二重拡散集積回路デバイスセルと、集積回路ｍｏｓｆｅｔセルの形成方法
US5506178A (en) * 1992-12-25 1996-04-09 Sony Corporation Process for forming gate silicon oxide film for MOS transistors

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05145027A (ja) * 1990-12-21 1993-06-11 Siliconix Inc シリコン集積回路の製造に於ける欠陥形成の制御方法、酸化膜の品質及び欠陥形成の制御方法、二重拡散集積回路デバイスセルと、集積回路ｍｏｓｆｅｔセルの形成方法
US5506178A (en) * 1992-12-25 1996-04-09 Sony Corporation Process for forming gate silicon oxide film for MOS transistors

Also Published As

Publication number Publication date
JPH0434299B2 (enExample) 1992-06-05

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