JPS57103554A - Control system of stack memory - Google Patents
Control system of stack memoryInfo
- Publication number
- JPS57103554A JPS57103554A JP18012280A JP18012280A JPS57103554A JP S57103554 A JPS57103554 A JP S57103554A JP 18012280 A JP18012280 A JP 18012280A JP 18012280 A JP18012280 A JP 18012280A JP S57103554 A JPS57103554 A JP S57103554A
- Authority
- JP
- Japan
- Prior art keywords
- region
- priority
- block region
- block
- information storing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
Abstract
PURPOSE:To ensure an effective application of a stack device, by selecting a block region to be replaced by referring to the priority of a process using the block region. CONSTITUTION:The priority of a process using a block region B1 is stored in a priority information storing region 3-1. After this, the priority of the process is stored in the same way in a priority information storing region 3-2 or 3-4 corresponding to a block region Bj (j: 1, 2, 3 and 4). If no block region allotted to the block of a stack designated by a stack access request exists, the contents of a priority information storing region 3-1-3-4 are supplied to a comparator 4. Thus the comparator 4 delivers the number of the block region showing the lowest value to an output part. As a result, the scheduling is made possible for the allotment of blocks with high efficiency without using any complicated circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18012280A JPS57103554A (en) | 1980-12-19 | 1980-12-19 | Control system of stack memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18012280A JPS57103554A (en) | 1980-12-19 | 1980-12-19 | Control system of stack memory |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57103554A true JPS57103554A (en) | 1982-06-28 |
Family
ID=16077798
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18012280A Pending JPS57103554A (en) | 1980-12-19 | 1980-12-19 | Control system of stack memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57103554A (en) |
-
1980
- 1980-12-19 JP JP18012280A patent/JPS57103554A/en active Pending
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