JPS5679354A - Memory access control system - Google Patents

Abstract

PURPOSE: To remarkably reduce a fault which is caused in the input/output unit system, by making it possible to assign the next cycle in accordance with intensity of a request even after the request has been stored in the memory access request stack.

CONSTITUTION: The memory access request information to which the waiting allowable time intervals from the request source 60-1W60-n are added is sent to the priority sequence deciding circuit 52, and the priority sequence is controlled. The request information to which the access right has been given is divided to the memory request information 111 and the time information 113, the information 111 is stored in the memory request stack, the information 113 is added to the time from the time counting part 55 by the adder 56 and becomes time information 115, and it is combined with the information 111 and stored in the stack 53. Subsequently, the time informations 301W304 output from the stack 53 are compared by the comparator 57, and the selector 58 is selected by the comparison result signal 116 showing the number of the stack in which the time information having the minimum value is stored. Accordingly, the memory access information 112 which is an output of the selector 58 becomes the request information of the highest urgency degree.

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