JPS56108123A - 1/n selection circuit - Google Patents

1/n selection circuit

Info

Publication number
JPS56108123A
JPS56108123A JP881580A JP881580A JPS56108123A JP S56108123 A JPS56108123 A JP S56108123A JP 881580 A JP881580 A JP 881580A JP 881580 A JP881580 A JP 881580A JP S56108123 A JPS56108123 A JP S56108123A
Authority
JP
Japan
Prior art keywords
counter
input
contents
multiplexer
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP881580A
Other languages
Japanese (ja)
Inventor
Hiroshi Dewa
Isao Saito
Hideo Yamauchi
Takenori Endo
Yoshio Inui
Akio Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP881580A priority Critical patent/JPS56108123A/en
Publication of JPS56108123A publication Critical patent/JPS56108123A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To enhance the process capacity, by providing a counter indicating the selecting position of input to a multiplexer. CONSTITUTION:The multiplexer 20 selects the input at the position where a coincidence is obtained to the contents of the n-notation counter 21. For instance, if the contents of the counter 21 are 2 at a certain time point, the multiplexer receives the information ''2'' from the signal line 50 indicating the input/output selecting positions to select the memory access request (signal line 32) out of the processor PR2. In the same way, the decoder 24 selects the output at the position where a coincidence is obtained to the contents of the counter 21. For instance, if the contents of the counter 21 are 2 at a certain time point, the memory access OK signal is given to the processor PR2 via the signal line 42. The synchronism of the clock controlling the processor is shorter than the memory cycle time, and the counter 21 is advanced by the short-cycle clock. Then the counter advance is inhibited until the process completes for the input signal in case any input signal is selected by the multiplexer.
JP881580A 1980-01-30 1980-01-30 1/n selection circuit Pending JPS56108123A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP881580A JPS56108123A (en) 1980-01-30 1980-01-30 1/n selection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP881580A JPS56108123A (en) 1980-01-30 1980-01-30 1/n selection circuit

Publications (1)

Publication Number Publication Date
JPS56108123A true JPS56108123A (en) 1981-08-27

Family

ID=11703306

Family Applications (1)

Application Number Title Priority Date Filing Date
JP881580A Pending JPS56108123A (en) 1980-01-30 1980-01-30 1/n selection circuit

Country Status (1)

Country Link
JP (1) JPS56108123A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6059464A (en) * 1983-09-12 1985-04-05 Nec Corp Bus request control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6059464A (en) * 1983-09-12 1985-04-05 Nec Corp Bus request control system

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