JPS57102038A - Marking device and marking method of semiconductor wafer - Google Patents

Marking device and marking method of semiconductor wafer

Info

Publication number
JPS57102038A
JPS57102038A JP17849580A JP17849580A JPS57102038A JP S57102038 A JPS57102038 A JP S57102038A JP 17849580 A JP17849580 A JP 17849580A JP 17849580 A JP17849580 A JP 17849580A JP S57102038 A JPS57102038 A JP S57102038A
Authority
JP
Japan
Prior art keywords
marking
wafer
inspected
metal wiring
semiconductor wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17849580A
Other languages
Japanese (ja)
Inventor
Akitoshi Tetsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP17849580A priority Critical patent/JPS57102038A/en
Publication of JPS57102038A publication Critical patent/JPS57102038A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To reduce scattering quantity of a metal wiring layer when marking of a semiconductor wafer is to be performed by a method wherein laser marking is performed using plural number of laser beams. CONSTITUTION:The wafer 5 to be inspected is fixed on a vacuum suck beas 4 of wafer prober. A probe 7 of probe card is made to come in contact with the wafer when inspection is to be performed. When the element to be inspected is disqualified, the laser beam 8 is irradiated to the surface of the element to be inspected, and the metal wiring on the surface of the element is fused to form an inferiority mark. When plural number of laser beams are used, because distribution of laser intensity can be unified, the inferiority mark can be formed without scattering the metal wiring layer.
JP17849580A 1980-12-17 1980-12-17 Marking device and marking method of semiconductor wafer Pending JPS57102038A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17849580A JPS57102038A (en) 1980-12-17 1980-12-17 Marking device and marking method of semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17849580A JPS57102038A (en) 1980-12-17 1980-12-17 Marking device and marking method of semiconductor wafer

Publications (1)

Publication Number Publication Date
JPS57102038A true JPS57102038A (en) 1982-06-24

Family

ID=16049445

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17849580A Pending JPS57102038A (en) 1980-12-17 1980-12-17 Marking device and marking method of semiconductor wafer

Country Status (1)

Country Link
JP (1) JPS57102038A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6559409B1 (en) * 1994-12-09 2003-05-06 Sgs-Thomson Microelectronics S.A. Method for marking integrated circuits with a laser

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6559409B1 (en) * 1994-12-09 2003-05-06 Sgs-Thomson Microelectronics S.A. Method for marking integrated circuits with a laser

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