JPS5699546A - Parallel processing microprocessor - Google Patents
Parallel processing microprocessorInfo
- Publication number
- JPS5699546A JPS5699546A JP107880A JP107880A JPS5699546A JP S5699546 A JPS5699546 A JP S5699546A JP 107880 A JP107880 A JP 107880A JP 107880 A JP107880 A JP 107880A JP S5699546 A JPS5699546 A JP S5699546A
- Authority
- JP
- Japan
- Prior art keywords
- rga
- circuit
- selecting
- rga15
- ram19
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/461—Saving or restoring of program or task context
- G06F9/463—Program control block organisation
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
PURPOSE:To enable to execute plural programs apparently by one processor, by providing the RGA save RAM storing plural register arrays and the RGA selecting circuit for selecting one RGA in the RAM. CONSTITUTION:The RGA save RAM19 storing plural contents of the register array RGA15, and the RGA selecting circuit 20 for selecting the RGA in the RAM19 are added to the microprocessor. The RGA15 is constituted of an accumulator, a register and a program counter. The circuit 20 generates the RGA selective signals SEL1-3 and the RGA read and write signals RGRG, RGWT from a clock signal CLK from the timing control circuit 18, and an instruction execution signal OPCLK which synchronizes with said signal and makes its signal level ''L'' for a given period of time, and also the contents of the run mode, and this circuit changes in order the contents of the RGA15 to the selected area of the RAM19 whenever 1 instruction is executed. In this way, plural programs can be executed in parallel.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP107880A JPS5699546A (en) | 1980-01-09 | 1980-01-09 | Parallel processing microprocessor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP107880A JPS5699546A (en) | 1980-01-09 | 1980-01-09 | Parallel processing microprocessor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5699546A true JPS5699546A (en) | 1981-08-10 |
Family
ID=11491459
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP107880A Pending JPS5699546A (en) | 1980-01-09 | 1980-01-09 | Parallel processing microprocessor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5699546A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6304957B1 (en) | 1993-02-26 | 2001-10-16 | Nippondenso Co., Ltd. | Multitask processing unit |
-
1980
- 1980-01-09 JP JP107880A patent/JPS5699546A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6304957B1 (en) | 1993-02-26 | 2001-10-16 | Nippondenso Co., Ltd. | Multitask processing unit |
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