JPS5746389A - Refresh control system - Google Patents
Refresh control systemInfo
- Publication number
- JPS5746389A JPS5746389A JP55122335A JP12233580A JPS5746389A JP S5746389 A JPS5746389 A JP S5746389A JP 55122335 A JP55122335 A JP 55122335A JP 12233580 A JP12233580 A JP 12233580A JP S5746389 A JPS5746389 A JP S5746389A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- register
- request
- refresh
- outputted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
Abstract
PURPOSE:To reduce the maximum access time to a register, by realizing a simultaneous execution of write/read processes and a refresh process to the register. CONSTITUTION:A memory request signal 2 supplied from outside reaches selection gates G1 and G2. If the request of that time is identical with a register request, the gate G2 is turned off since no memory cycle signal 7 is produced. Then the signal 2 passes through the gate G1, and a register start signal 3 is outputted and processed. Accordingly the signal 2 is not supplied to a priority deciding circuit 9 on the register request, and as a result both the signal 3 and a refresh selection signal 11 are outputted when a refresh request 10 is produced concurrently. Thus both the refresh and register processes are carried out in parallel.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55122335A JPS5746389A (en) | 1980-09-05 | 1980-09-05 | Refresh control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55122335A JPS5746389A (en) | 1980-09-05 | 1980-09-05 | Refresh control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5746389A true JPS5746389A (en) | 1982-03-16 |
Family
ID=14833416
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55122335A Pending JPS5746389A (en) | 1980-09-05 | 1980-09-05 | Refresh control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5746389A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6168661B1 (en) | 1998-04-10 | 2001-01-02 | Johnson Controls Technology Company | Battery cell coating apparatus and method |
-
1980
- 1980-09-05 JP JP55122335A patent/JPS5746389A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6168661B1 (en) | 1998-04-10 | 2001-01-02 | Johnson Controls Technology Company | Battery cell coating apparatus and method |
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