JPS5691467A - Dhd sealed semiconductor - Google Patents

Dhd sealed semiconductor

Info

Publication number
JPS5691467A
JPS5691467A JP16837379A JP16837379A JPS5691467A JP S5691467 A JPS5691467 A JP S5691467A JP 16837379 A JP16837379 A JP 16837379A JP 16837379 A JP16837379 A JP 16837379A JP S5691467 A JPS5691467 A JP S5691467A
Authority
JP
Japan
Prior art keywords
poly
film
layer
diffusion
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16837379A
Other languages
Japanese (ja)
Inventor
Kohei Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP16837379A priority Critical patent/JPS5691467A/en
Publication of JPS5691467A publication Critical patent/JPS5691467A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]

Abstract

PURPOSE:To stabilize characteristics and raise reliability by forming a metallic film over the surface of an Si substrate with a polycrystalline Si layer provided therebetween and a silver plating electrodes thereon. CONSTITUTION:P-diffusion is made on the surface of an n type monocrystalline Si substrate 5 using an oxide film 6 as mask and a poly-Si layer 9 is formed over the whole surface of the diffusion. Next, a contact is made by spattering or depositing a metal 10 such as Au-Ga on a poly-Si layer. Thereafter the unnecessary portion of Au-Ga film is removed by photo-etching. Next, an Ag bump electrode 11 is formed through electric Ag plating using the Au-Ga film as anode. Thereby, the reactive alloying of Poly-Si-metal progresses so that sufficient bump strength can be obtained.
JP16837379A 1979-12-26 1979-12-26 Dhd sealed semiconductor Pending JPS5691467A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16837379A JPS5691467A (en) 1979-12-26 1979-12-26 Dhd sealed semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16837379A JPS5691467A (en) 1979-12-26 1979-12-26 Dhd sealed semiconductor

Publications (1)

Publication Number Publication Date
JPS5691467A true JPS5691467A (en) 1981-07-24

Family

ID=15866885

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16837379A Pending JPS5691467A (en) 1979-12-26 1979-12-26 Dhd sealed semiconductor

Country Status (1)

Country Link
JP (1) JPS5691467A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60169168A (en) * 1984-02-13 1985-09-02 Rohm Co Ltd Electrode structure of semiconductor element
JPS6243168A (en) * 1985-08-21 1987-02-25 Rohm Co Ltd Individual semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5010565A (en) * 1973-05-24 1975-02-03
JPS5269561A (en) * 1975-12-08 1977-06-09 Hitachi Ltd Electrode of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5010565A (en) * 1973-05-24 1975-02-03
JPS5269561A (en) * 1975-12-08 1977-06-09 Hitachi Ltd Electrode of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60169168A (en) * 1984-02-13 1985-09-02 Rohm Co Ltd Electrode structure of semiconductor element
JPS6243168A (en) * 1985-08-21 1987-02-25 Rohm Co Ltd Individual semiconductor device

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