JPS5690356A - Information processing unit - Google Patents

Information processing unit

Info

Publication number
JPS5690356A
JPS5690356A JP16775479A JP16775479A JPS5690356A JP S5690356 A JPS5690356 A JP S5690356A JP 16775479 A JP16775479 A JP 16775479A JP 16775479 A JP16775479 A JP 16775479A JP S5690356 A JPS5690356 A JP S5690356A
Authority
JP
Japan
Prior art keywords
data
memory
register
bits
main memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16775479A
Other languages
Japanese (ja)
Inventor
Tsuneo Kinoshita
Fumitaka Sato
Isamu Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP16775479A priority Critical patent/JPS5690356A/en
Publication of JPS5690356A publication Critical patent/JPS5690356A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To easily realize the memory boundary control by means of a simple constitution, by selectively addressing two memory banks of the main memory so that it can be controlled to write a data.
CONSTITUTION: When a write data is transferred from the 1 chip CPU101, the memory data register 204 or 206 is selected in accordance with the value of the lower rank bit of the memory address register 206. This selected is sent to the main memory side through the C-bus 103 and the memory data line MDL. In the main memory side, the data is written by N bits each to the first or second memory bank of the main memory in accordance with the lower rank bit of the register 206. Also, in case of read designation, the first and second memory banks are read out and controlled at the same time, and a read data of 2N bits each is read out to the line MDL. As for this data, the data of the high rank N bits, and that of the lower rank N bits are stored through the bus 103 in the register 204 and the register 205, respectively.
COPYRIGHT: (C)1981,JPO&Japio
JP16775479A 1979-12-24 1979-12-24 Information processing unit Pending JPS5690356A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16775479A JPS5690356A (en) 1979-12-24 1979-12-24 Information processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16775479A JPS5690356A (en) 1979-12-24 1979-12-24 Information processing unit

Publications (1)

Publication Number Publication Date
JPS5690356A true JPS5690356A (en) 1981-07-22

Family

ID=15855471

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16775479A Pending JPS5690356A (en) 1979-12-24 1979-12-24 Information processing unit

Country Status (1)

Country Link
JP (1) JPS5690356A (en)

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