JPS5473527A - Buffer memory control system - Google Patents
Buffer memory control systemInfo
- Publication number
- JPS5473527A JPS5473527A JP14087577A JP14087577A JPS5473527A JP S5473527 A JPS5473527 A JP S5473527A JP 14087577 A JP14087577 A JP 14087577A JP 14087577 A JP14087577 A JP 14087577A JP S5473527 A JPS5473527 A JP S5473527A
- Authority
- JP
- Japan
- Prior art keywords
- register
- buffer memory
- directory
- address
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
- Advance Control (AREA)
Abstract
PURPOSE: To transfer the store data to the main memory as well as to write it into the buffer memory when the data designated by the store address exists in the buffer memory, and then to secure the coincidence of the contents between the both memories.
CONSTITUTION: Store address SA sent from memory control unit 6 is set to directory address register 9 via SA register 7, and an index is given to the directory via the lower bit of SA. The higher address delivered from directory 1 is compared with the higher address information of SA through coincidence circuit 19. In case SA has a coincidence within directory 1, the contents of data buffer data register 18 is shifted to buffer memory writing register 12 to be then written into buffer memory 13. The memory place is designated by register 10 in which the store address is stored.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14087577A JPS5473527A (en) | 1977-11-24 | 1977-11-24 | Buffer memory control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14087577A JPS5473527A (en) | 1977-11-24 | 1977-11-24 | Buffer memory control system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5473527A true JPS5473527A (en) | 1979-06-12 |
| JPS5717310B2 JPS5717310B2 (en) | 1982-04-09 |
Family
ID=15278780
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14087577A Granted JPS5473527A (en) | 1977-11-24 | 1977-11-24 | Buffer memory control system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5473527A (en) |
-
1977
- 1977-11-24 JP JP14087577A patent/JPS5473527A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5717310B2 (en) | 1982-04-09 |
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