JPS5688339A - Dhd-sealed semiconductor device - Google Patents

Dhd-sealed semiconductor device

Info

Publication number
JPS5688339A
JPS5688339A JP16556579A JP16556579A JPS5688339A JP S5688339 A JPS5688339 A JP S5688339A JP 16556579 A JP16556579 A JP 16556579A JP 16556579 A JP16556579 A JP 16556579A JP S5688339 A JPS5688339 A JP S5688339A
Authority
JP
Japan
Prior art keywords
substrate
electrode
dhd
semiconductor device
evaporated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16556579A
Other languages
Japanese (ja)
Other versions
JPS6346984B2 (en
Inventor
Kohei Yamada
Hiroshi Ikeda
Hideo Tanbara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP16556579A priority Critical patent/JPS5688339A/en
Publication of JPS5688339A publication Critical patent/JPS5688339A/en
Publication of JPS6346984B2 publication Critical patent/JPS6346984B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To obtain an electrode structure having high heat resistance, preferable adherence and excellent strength by forming an Ag-plated electrode through Ti and Pd films on the main surface of an Si substrate. CONSTITUTION:A p type layer 4 is formed on an n type epitaxial layer of an n<+> type Si substrate, a window is opened at an SiO2 film 5, and Ti 5 having preferable adherence with the Si and the SiO2 and high heat resistance is evaporated thereon. Subsequently, a heat resistant Pd 6 for preventing the oxidation of the Ti is evaporated thereon. Then, a PSG 7 is covered thereon, is etched to open a window thereat, and the PSG surface is thus roughed. An Au-Ag electrode 9 is formed on the back surface of the substrate, and an Ag bump electrode 10 is formed by an electric plating on the front surface of the substrate, thereby increasing the adhering strength. When this diode element is inserted between studs 12 in a glass tube 11 and the tube is sealed at a temperature higher than 600 deg.C, there can be obtained the DHD-sealed semiconductor device having a highly reliable electrode structure.
JP16556579A 1979-12-21 1979-12-21 Dhd-sealed semiconductor device Granted JPS5688339A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16556579A JPS5688339A (en) 1979-12-21 1979-12-21 Dhd-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16556579A JPS5688339A (en) 1979-12-21 1979-12-21 Dhd-sealed semiconductor device

Publications (2)

Publication Number Publication Date
JPS5688339A true JPS5688339A (en) 1981-07-17
JPS6346984B2 JPS6346984B2 (en) 1988-09-20

Family

ID=15814771

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16556579A Granted JPS5688339A (en) 1979-12-21 1979-12-21 Dhd-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPS5688339A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0144887A2 (en) * 1983-11-30 1985-06-19 Siemens Aktiengesellschaft Semiconductor component having metallic bump contacts and multilayer interconnection
US4916084A (en) * 1987-07-13 1990-04-10 Kabushiki Kaisha Toshiba Method for manufacturing MOS semiconductor devices
EP0628998A1 (en) * 1993-05-28 1994-12-14 Kabushiki Kaisha Toshiba Wiring layer for semi conductor device and method for manufacturing the same
US5656542A (en) * 1993-05-28 1997-08-12 Kabushiki Kaisha Toshiba Method for manufacturing wiring in groove
JP2008205249A (en) * 2007-02-21 2008-09-04 Renesas Technology Corp Method of fabricating semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4915382A (en) * 1972-03-27 1974-02-09
JPS4940108A (en) * 1972-08-17 1974-04-15
JPS5487470A (en) * 1977-12-24 1979-07-11 Fuji Electric Co Ltd Manufacture of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4915382A (en) * 1972-03-27 1974-02-09
JPS4940108A (en) * 1972-08-17 1974-04-15
JPS5487470A (en) * 1977-12-24 1979-07-11 Fuji Electric Co Ltd Manufacture of semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0144887A2 (en) * 1983-11-30 1985-06-19 Siemens Aktiengesellschaft Semiconductor component having metallic bump contacts and multilayer interconnection
EP0144887A3 (en) * 1983-11-30 1985-07-17 Siemens Aktiengesellschaft Semiconductor component having metallic bump contacts and multilayer interconnection
US4916084A (en) * 1987-07-13 1990-04-10 Kabushiki Kaisha Toshiba Method for manufacturing MOS semiconductor devices
EP0628998A1 (en) * 1993-05-28 1994-12-14 Kabushiki Kaisha Toshiba Wiring layer for semi conductor device and method for manufacturing the same
US5500559A (en) * 1993-05-28 1996-03-19 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US5656542A (en) * 1993-05-28 1997-08-12 Kabushiki Kaisha Toshiba Method for manufacturing wiring in groove
JP2008205249A (en) * 2007-02-21 2008-09-04 Renesas Technology Corp Method of fabricating semiconductor device

Also Published As

Publication number Publication date
JPS6346984B2 (en) 1988-09-20

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