JPS5674951A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5674951A
JPS5674951A JP15065179A JP15065179A JPS5674951A JP S5674951 A JPS5674951 A JP S5674951A JP 15065179 A JP15065179 A JP 15065179A JP 15065179 A JP15065179 A JP 15065179A JP S5674951 A JPS5674951 A JP S5674951A
Authority
JP
Japan
Prior art keywords
tip
electrode
wiring layer
lead
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15065179A
Other languages
Japanese (ja)
Inventor
Joji Okada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15065179A priority Critical patent/JPS5674951A/en
Publication of JPS5674951A publication Critical patent/JPS5674951A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49531—Additional leads the additional leads being a wiring board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To eliminate a tab and dispense with line bonding by arranging wiring between a tip and a lead, using an insulative tip support plate equipped with a wiring layer on the surface. CONSTITUTION:A wiring layer 13 corresponding to an electrode 11 of tip 10 is formed on a polyimido resin plate 12 capable of intercepting ''a'' ray with the help of printing, etc. The tip 10 with the electrode 11 turned downward is placed on a support plate 12, and is thermally treated to connect the electrode 11 and the wiring layer 13. Next, a lead frame without tab and wiring 13 are connected together as they correspond to each other. After this procedure, resin 15 is sealed in an usual manner, and lead 14 is separated from the frame and completed by bending. Under this constitution, it is possible to significantly reduce a required number of manhours.
JP15065179A 1979-11-22 1979-11-22 Semiconductor device Pending JPS5674951A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15065179A JPS5674951A (en) 1979-11-22 1979-11-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15065179A JPS5674951A (en) 1979-11-22 1979-11-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5674951A true JPS5674951A (en) 1981-06-20

Family

ID=15501495

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15065179A Pending JPS5674951A (en) 1979-11-22 1979-11-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5674951A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63114222A (en) * 1986-10-31 1988-05-19 Texas Instr Japan Ltd Semiconductor device
US5319242A (en) * 1992-03-18 1994-06-07 Motorola, Inc. Semiconductor package having an exposed die surface
WO1995008856A1 (en) * 1993-09-20 1995-03-30 Tessera, Inc. Method of forming interface between die and chip carrier

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63114222A (en) * 1986-10-31 1988-05-19 Texas Instr Japan Ltd Semiconductor device
US5319242A (en) * 1992-03-18 1994-06-07 Motorola, Inc. Semiconductor package having an exposed die surface
WO1995008856A1 (en) * 1993-09-20 1995-03-30 Tessera, Inc. Method of forming interface between die and chip carrier
US5477611A (en) * 1993-09-20 1995-12-26 Tessera, Inc. Method of forming interface between die and chip carrier

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