JPS5673441A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5673441A
JPS5673441A JP15002979A JP15002979A JPS5673441A JP S5673441 A JPS5673441 A JP S5673441A JP 15002979 A JP15002979 A JP 15002979A JP 15002979 A JP15002979 A JP 15002979A JP S5673441 A JPS5673441 A JP S5673441A
Authority
JP
Japan
Prior art keywords
layer
junction surface
depletion
mesa
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15002979A
Other languages
Japanese (ja)
Inventor
Kenichi Goto
Masafumi Miyagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15002979A priority Critical patent/JPS5673441A/en
Publication of JPS5673441A publication Critical patent/JPS5673441A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To obtain the high-tension resistance for the subject semiconductor device by a method wherein a junction surface is provided in such a manner that one of layers is annually surrounding the other layer, a main junction surface is formed by performing a mesa etching on one of the layers in such way that the edge of the junction surface of the other layer is located on the mesa-side circumferential surface. CONSTITUTION:The P<+> layer 41 of an N type substrate 2 is projected by performing a mesa etching, the junction end of a P<+> layer 42 is extended to a mesa- side surface 5 and it is annularly surrounding the outside of the layer 41. The edge of the main junction surface 11 and the edge of an auxiliary junction surface 12 are covered by a protective film 3. When an inverse voltage is applied, a depletion layer width xd(V) is generated, and when a depletion layer 61 is enlarged to the lateral direction and reaches to the P<+> layer 42, a floating potential is induced on the layer 42, a new depletion layer 62 is generated on the peripheral section of the auxiliary junction surface 12, and a depletion layer width xd(L) is generated by the composition of the above two depletion layers, thereby enabling to weaken the surface field strength and to increase the breakdown voltage.
JP15002979A 1979-11-21 1979-11-21 Semiconductor device Pending JPS5673441A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15002979A JPS5673441A (en) 1979-11-21 1979-11-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15002979A JPS5673441A (en) 1979-11-21 1979-11-21 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5673441A true JPS5673441A (en) 1981-06-18

Family

ID=15487935

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15002979A Pending JPS5673441A (en) 1979-11-21 1979-11-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5673441A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009055063A (en) * 2003-04-09 2009-03-12 Kansai Electric Power Co Inc:The Gate turnoff thyristor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009055063A (en) * 2003-04-09 2009-03-12 Kansai Electric Power Co Inc:The Gate turnoff thyristor

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