JPS567160A - System controller - Google Patents

System controller

Info

Publication number
JPS567160A
JPS567160A JP8213779A JP8213779A JPS567160A JP S567160 A JPS567160 A JP S567160A JP 8213779 A JP8213779 A JP 8213779A JP 8213779 A JP8213779 A JP 8213779A JP S567160 A JPS567160 A JP S567160A
Authority
JP
Japan
Prior art keywords
port
access
ports
permission
chc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8213779A
Other languages
Japanese (ja)
Inventor
Shigeo Kimuro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8213779A priority Critical patent/JPS567160A/en
Publication of JPS567160A publication Critical patent/JPS567160A/en
Pending legal-status Critical Current

Links

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  • Memory System (AREA)

Abstract

PURPOSE: To increase the process eficiency for the system as a whole, by decreasing the number of the delay circuit of the specific port among plural number of ports and then increasing the access speed of only the specific port.
CONSTITUTION: When memory access requests arise from CPU101 and channel control unit CHC102, the address information and the request signal are sent to ports 201 and 202 corresponding to system control unit 104. The request signal is sent to request reception deciding circuit 203 to carry out the priority decision among ports, and then the access is allowed only to the high-priority port. When the access permission is given to port 201, FF204 is set with gate circuit 205 opened. And then the permission is transferred immediately to main memory device 103 via memory port 208. When the access permission is given to CHC port 202, gate circuits 205 and 206 are switched toward the CHC port side. And then the control signal is delayed through delay circuit 207 to be transferred to device 103 along with the address information.
COPYRIGHT: (C)1981,JPO&Japio
JP8213779A 1979-06-29 1979-06-29 System controller Pending JPS567160A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8213779A JPS567160A (en) 1979-06-29 1979-06-29 System controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8213779A JPS567160A (en) 1979-06-29 1979-06-29 System controller

Publications (1)

Publication Number Publication Date
JPS567160A true JPS567160A (en) 1981-01-24

Family

ID=13766023

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8213779A Pending JPS567160A (en) 1979-06-29 1979-06-29 System controller

Country Status (1)

Country Link
JP (1) JPS567160A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60205767A (en) * 1984-03-30 1985-10-17 Fujitsu Ltd Data processor
JPS61150054A (en) * 1984-12-20 1986-07-08 ハネウエル・インコーポレーテツド Data processor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60205767A (en) * 1984-03-30 1985-10-17 Fujitsu Ltd Data processor
JPS61150054A (en) * 1984-12-20 1986-07-08 ハネウエル・インコーポレーテツド Data processor

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